ARM: dts: zx: add an initial zx296702 dts and doc
Add initial dts file and document for ZX296702 and board ZX296702-AD1. More peripherals will be added later. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Kevin Hilman <khilman@linaro.org>
This commit is contained in:
Jun Nie
Kevin Hilman
parent
5a46580812
commit
d5553cb05a
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@ -0,0 +1,15 @@
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ZTE platforms device tree bindings
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---------------------------------------
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- ZX296702 board:
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Required root node properties:
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- compatible = "zte,zx296702-ad1", "zte,zx296702"
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System management required properties:
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- compatible = "zte,sysctrl"
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Low power management required properties:
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- compatible = "zte,zx296702-pcu"
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Bus matrix required properties:
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- compatible = "zte,zx-bus-matrix"
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@ -0,0 +1,35 @@
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Device Tree Clock bindings for ZTE zx296702
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be one of the following:
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"zte,zx296702-topcrm-clk":
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zx296702 top clock selection, divider and gating
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"zte,zx296702-lsp0crpm-clk" and
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"zte,zx296702-lsp1crpm-clk":
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zx296702 device level clock selection and gating
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- reg: Address and length of the register set
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296702-clock.h
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for the full list of zx296702 clock IDs.
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topclk: topcrm@0x09800000 {
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compatible = "zte,zx296702-topcrm-clk";
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reg = <0x09800000 0x1000>;
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#clock-cells = <1>;
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};
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uart0: serial@0x09405000 {
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compatible = "zte,zx296702-uart";
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reg = <0x09405000 0x1000>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&lsp1clk ZX296702_UART0_PCLK>;
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status = "disabled";
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};
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@ -1,7 +1,7 @@
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* ARM AMBA Primecell PL011 serial UART
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Required properties:
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- compatible: must be "arm,primecell", "arm,pl011"
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- compatible: must be "arm,primecell", "arm,pl011", "zte,zx296702-uart"
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- reg: exactly one register range with length 0x1000
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- interrupts: exactly one interrupt specifier
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@ -211,3 +211,4 @@ xillybus Xillybus Ltd.
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xlnx Xilinx
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zyxel ZyXEL Communications Corp.
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zarlink Zarlink Semiconductor
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zte ZTE Corp.
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@ -660,6 +660,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
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mt6592-evb.dtb \
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mt8127-moose.dtb \
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mt8135-evbp1.dtb
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dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
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endif
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always := $(dtb-y)
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@ -0,0 +1,48 @@
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/dts-v1/;
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#include "zx296702.dtsi"
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/ {
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model = "ZTE ZX296702 AD1 Board";
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compatible = "zte,zx296702-ad1", "zte,zx296702";
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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};
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memory {
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reg = <0x50000000 0x20000000>;
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};
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};
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&mmc0 {
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num-slots = <1>;
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supports-highspeed;
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non-removable;
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disable-wp;
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status = "okay";
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slot@0 {
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reg = <0>;
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bus-width = <4>;
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};
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};
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&mmc1 {
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num-slots = <1>;
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supports-highspeed;
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non-removable;
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disable-wp;
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status = "okay";
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slot@0 {
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reg = <0>;
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bus-width = <8>;
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};
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};
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&uart0 {
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status = "okay";
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};
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@ -0,0 +1,139 @@
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/zx296702-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "zte,zx296702-smp";
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cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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next-level-cache = <&l2cc>;
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reg = <0>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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next-level-cache = <&l2cc>;
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reg = <1>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&intc>;
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ranges;
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matrix: bus-matrix@400000 {
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compatible = "zte,zx-bus-matrix";
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reg = <0x00400000 0x1000>;
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};
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intc: interrupt-controller@00801000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-controller;
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reg = <0x00801000 0x1000>,
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<0x00800100 0x100>;
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};
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global_timer: timer@008000200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x00800200 0x20>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&intc>;
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clocks = <&topclk ZX296702_A9_PERIPHCLK>;
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};
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l2cc: l2-cache-controller@0x00c00000 {
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compatible = "arm,pl310-cache";
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reg = <0x00c00000 0x1000>;
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cache-unified;
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cache-level = <2>;
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arm,data-latency = <1 1 1>;
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arm,tag-latency = <1 1 1>;
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arm,double-linefill = <1>;
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arm,double-linefill-incr = <0>;
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};
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pcu: pcu@0xa0008000 {
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compatible = "zte,zx296702-pcu";
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reg = <0xa0008000 0x1000>;
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};
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topclk: topclk@0x09800000 {
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compatible = "zte,zx296702-topcrm-clk";
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reg = <0x09800000 0x1000>;
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#clock-cells = <1>;
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};
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lsp1clk: lsp1clk@0x09400000 {
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compatible = "zte,zx296702-lsp1crpm-clk";
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reg = <0x09400000 0x1000>;
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#clock-cells = <1>;
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};
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lsp0clk: lsp0clk@0x0b000000 {
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compatible = "zte,zx296702-lsp0crpm-clk";
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reg = <0x0b000000 0x1000>;
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#clock-cells = <1>;
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};
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uart0: serial@0x09405000 {
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compatible = "zte,zx296702-uart";
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reg = <0x09405000 0x1000>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&lsp1clk ZX296702_UART0_WCLK>;
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status = "disabled";
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};
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uart1: serial@0x09406000 {
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compatible = "zte,zx296702-uart";
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reg = <0x09406000 0x1000>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&lsp1clk ZX296702_UART1_WCLK>;
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status = "disabled";
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};
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mmc0: mmc@0x09408000 {
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compatible = "snps,dw-mshc";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x09408000 0x1000>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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fifo-depth = <32>;
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clocks = <&lsp1clk ZX296702_SDMMC0_PCLK>,
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<&lsp1clk ZX296702_SDMMC0_WCLK>;
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clock-names = "biu", "ciu";
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status = "disabled";
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};
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mmc1: mmc@0x0b003000 {
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compatible = "snps,dw-mshc";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0b003000 0x1000>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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fifo-depth = <32>;
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clocks = <&lsp0clk ZX296702_SDMMC1_PCLK>,
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<&lsp0clk ZX296702_SDMMC1_WCLK>;
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clock-names = "biu", "ciu";
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status = "disabled";
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};
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sysctrl: sysctrl@0xa0007000 {
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compatible = "zte,sysctrl", "syscon";
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reg = <0xa0007000 0x1000>;
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};
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};
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};
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