Merge branches 'clk-rockchip', 'clk-ingenic', 'clk-bindings', 'clk-samsung' and 'clk-stm' into clk-next
- Mark some clks critical on Ingenic X1000 - Add STM32MP13 RCC driver (Reset Clock Controller) * clk-rockchip: dt-bindings: clock: convert rockchip,rk3368-cru.txt to YAML dt-bindings: clock: convert rockchip,rk3228-cru.txt to YAML dt-bindings: clock: convert rockchip,rk3036-cru.txt to YAML dt-bindings: clock: convert rockchip,rk3308-cru.txt to YAML dt-bindings: clock: convert rockchip,px30-cru.txt to YAML dt-bindings: clock: convert rockchip,rk3188-cru.txt to YAML dt-bindings: clock: convert rockchip,rk3288-cru.txt to YAML dt-bindings: clock: convert rockchip,rv1108-cru.txt to YAML dt-binding: clock: Add missing rk3568 cru bindings clk: rockchip: Mark hclk_vo as critical on rk3568 dt-bindings: clock: fix rk3399 cru clock issues dt-bindings: clock: use generic node name for pmucru example in rockchip,rk3399-cru.yaml dt-bindings: clock: replace a maintainer for rockchip,rk3399-cru.yaml dt-bindings: clock: fix some conversion style issues for rockchip,rk3399-cru.yaml * clk-ingenic: clk: ingenic-tcu: Fix missing TCU clock for X1000 SoCs mips: ingenic: Do not manually reference the CPU clock clk: ingenic: Mark critical clocks in Ingenic SoCs clk: ingenic: Allow specifying common clock flags * clk-bindings: dt-bindings: clock: Replace common binding with link to schema * clk-samsung: dt-bindings: clock: exynosautov9: correct count of NR_CLK clk: samsung: exynosautov9: add cmu_peric1 clock support clk: samsung: exynosautov9: add cmu_peric0 clock support clk: samsung: exynosautov9: add cmu_fsys2 clock support clk: samsung: exynosautov9: add cmu_busmc clock support clk: samsung: exynosautov9: add cmu_peris clock support clk: samsung: exynosautov9: add cmu_core clock support clk: samsung: add top clock support for Exynos Auto v9 SoC dt-bindings: clock: add Exynos Auto v9 SoC CMU bindings dt-bindings: clock: add clock binding definitions for Exynos Auto v9 * clk-stm: clk: stm32mp13: add safe mux management clk: stm32mp13: add multi mux function clk: stm32mp13: add all STM32MP13 kernel clocks clk: stm32mp13: add all STM32MP13 peripheral clocks clk: stm32mp13: manage secured clocks clk: stm32mp13: add composite clock clk: stm32mp13: add stm32 divider clock clk: stm32mp13: add stm32_gate management clk: stm32mp13: add stm32_mux clock management clk: stm32: Introduce STM32MP13 RCC drivers (Reset Clock Controller) dt-bindings: rcc: stm32: add new compatible for STM32MP13 SoC
This commit is contained in:
Stephen Boyd
commit
d75c26a926
|
|
@ -1,186 +1,2 @@
|
|||
This binding is a work-in-progress, and are based on some experimental
|
||||
work by benh[1].
|
||||
|
||||
Sources of clock signal can be represented by any node in the device
|
||||
tree. Those nodes are designated as clock providers. Clock consumer
|
||||
nodes use a phandle and clock specifier pair to connect clock provider
|
||||
outputs to clock inputs. Similar to the gpio specifiers, a clock
|
||||
specifier is an array of zero, one or more cells identifying the clock
|
||||
output on a device. The length of a clock specifier is defined by the
|
||||
value of a #clock-cells property in the clock provider node.
|
||||
|
||||
[1] https://patchwork.ozlabs.org/patch/31551/
|
||||
|
||||
==Clock providers==
|
||||
|
||||
Required properties:
|
||||
#clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
|
||||
with a single clock output and 1 for nodes with multiple
|
||||
clock outputs.
|
||||
|
||||
Optional properties:
|
||||
clock-output-names: Recommended to be a list of strings of clock output signal
|
||||
names indexed by the first cell in the clock specifier.
|
||||
However, the meaning of clock-output-names is domain
|
||||
specific to the clock provider, and is only provided to
|
||||
encourage using the same meaning for the majority of clock
|
||||
providers. This format may not work for clock providers
|
||||
using a complex clock specifier format. In those cases it
|
||||
is recommended to omit this property and create a binding
|
||||
specific names property.
|
||||
|
||||
Clock consumer nodes must never directly reference
|
||||
the provider's clock-output-names property.
|
||||
|
||||
For example:
|
||||
|
||||
oscillator {
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "ckil", "ckih";
|
||||
};
|
||||
|
||||
- this node defines a device with two clock outputs, the first named
|
||||
"ckil" and the second named "ckih". Consumer nodes always reference
|
||||
clocks by index. The names should reflect the clock output signal
|
||||
names for the device.
|
||||
|
||||
clock-indices: If the identifying number for the clocks in the node
|
||||
is not linear from zero, then this allows the mapping of
|
||||
identifiers into the clock-output-names array.
|
||||
|
||||
For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
|
||||
|
||||
oscillator {
|
||||
compatible = "myclocktype";
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <1>, <3>;
|
||||
clock-output-names = "clka", "clkb";
|
||||
}
|
||||
|
||||
This ensures we do not have any empty strings in clock-output-names
|
||||
|
||||
|
||||
==Clock consumers==
|
||||
|
||||
Required properties:
|
||||
clocks: List of phandle and clock specifier pairs, one pair
|
||||
for each clock input to the device. Note: if the
|
||||
clock provider specifies '0' for #clock-cells, then
|
||||
only the phandle portion of the pair will appear.
|
||||
|
||||
Optional properties:
|
||||
clock-names: List of clock input name strings sorted in the same
|
||||
order as the clocks property. Consumers drivers
|
||||
will use clock-names to match clock input names
|
||||
with clocks specifiers.
|
||||
clock-ranges: Empty property indicating that child nodes can inherit named
|
||||
clocks from this node. Useful for bus nodes to provide a
|
||||
clock to their children.
|
||||
|
||||
For example:
|
||||
|
||||
device {
|
||||
clocks = <&osc 1>, <&ref 0>;
|
||||
clock-names = "baud", "register";
|
||||
};
|
||||
|
||||
|
||||
This represents a device with two clock inputs, named "baud" and "register".
|
||||
The baud clock is connected to output 1 of the &osc device, and the register
|
||||
clock is connected to output 0 of the &ref.
|
||||
|
||||
==Example==
|
||||
|
||||
/* external oscillator */
|
||||
osc: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32678>;
|
||||
clock-output-names = "osc";
|
||||
};
|
||||
|
||||
/* phase-locked-loop device, generates a higher frequency clock
|
||||
* from the external oscillator reference */
|
||||
pll: pll@4c000 {
|
||||
compatible = "vendor,some-pll-interface"
|
||||
#clock-cells = <1>;
|
||||
clocks = <&osc 0>;
|
||||
clock-names = "ref";
|
||||
reg = <0x4c000 0x1000>;
|
||||
clock-output-names = "pll", "pll-switched";
|
||||
};
|
||||
|
||||
/* UART, using the low frequency oscillator for the baud clock,
|
||||
* and the high frequency switched PLL output for register
|
||||
* clocking */
|
||||
uart@a000 {
|
||||
compatible = "fsl,imx-uart";
|
||||
reg = <0xa000 0x1000>;
|
||||
interrupts = <33>;
|
||||
clocks = <&osc 0>, <&pll 1>;
|
||||
clock-names = "baud", "register";
|
||||
};
|
||||
|
||||
This DT fragment defines three devices: an external oscillator to provide a
|
||||
low-frequency reference clock, a PLL device to generate a higher frequency
|
||||
clock signal, and a UART.
|
||||
|
||||
* The oscillator is fixed-frequency, and provides one clock output, named "osc".
|
||||
* The PLL is both a clock provider and a clock consumer. It uses the clock
|
||||
signal generated by the external oscillator, and provides two output signals
|
||||
("pll" and "pll-switched").
|
||||
* The UART has its baud clock connected the external oscillator and its
|
||||
register clock connected to the PLL clock (the "pll-switched" signal)
|
||||
|
||||
==Assigned clock parents and rates==
|
||||
|
||||
Some platforms may require initial configuration of default parent clocks
|
||||
and clock frequencies. Such a configuration can be specified in a device tree
|
||||
node through assigned-clocks, assigned-clock-parents and assigned-clock-rates
|
||||
properties. The assigned-clock-parents property should contain a list of parent
|
||||
clocks in the form of a phandle and clock specifier pair and the
|
||||
assigned-clock-rates property should contain a list of frequencies in Hz. Both
|
||||
these properties should correspond to the clocks listed in the assigned-clocks
|
||||
property.
|
||||
|
||||
To skip setting parent or rate of a clock its corresponding entry should be
|
||||
set to 0, or can be omitted if it is not followed by any non-zero entry.
|
||||
|
||||
uart@a000 {
|
||||
compatible = "fsl,imx-uart";
|
||||
reg = <0xa000 0x1000>;
|
||||
...
|
||||
clocks = <&osc 0>, <&pll 1>;
|
||||
clock-names = "baud", "register";
|
||||
|
||||
assigned-clocks = <&clkcon 0>, <&pll 2>;
|
||||
assigned-clock-parents = <&pll 2>;
|
||||
assigned-clock-rates = <0>, <460800>;
|
||||
};
|
||||
|
||||
In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and
|
||||
the <&pll 2> clock is assigned a frequency value of 460800 Hz.
|
||||
|
||||
Configuring a clock's parent and rate through the device node that consumes
|
||||
the clock can be done only for clocks that have a single user. Specifying
|
||||
conflicting parent or rate configuration in multiple consumer nodes for
|
||||
a shared clock is forbidden.
|
||||
|
||||
Configuration of common clocks, which affect multiple consumer devices can
|
||||
be similarly specified in the clock provider node.
|
||||
|
||||
==Protected clocks==
|
||||
|
||||
Some platforms or firmwares may not fully expose all the clocks to the OS, such
|
||||
as in situations where those clks are used by drivers running in ARM secure
|
||||
execution levels. Such a configuration can be specified in device tree with the
|
||||
protected-clocks property in the form of a clock specifier list. This property should
|
||||
only be specified in the node that is providing the clocks being protected:
|
||||
|
||||
clock-controller@a000f000 {
|
||||
compatible = "vendor,clk95;
|
||||
reg = <0xa000f000 0x1000>
|
||||
#clocks-cells = <1>;
|
||||
...
|
||||
protected-clocks = <UART3_CLK>, <SPI5_CLK>;
|
||||
};
|
||||
This file has moved to the clock binding schema:
|
||||
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml
|
||||
|
|
|
|||
|
|
@ -1,70 +0,0 @@
|
|||
* Rockchip PX30 Clock and Reset Unit
|
||||
|
||||
The PX30 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: PMU for CRU should be "rockchip,px30-pmu-cru"
|
||||
- compatible: CRU should be "rockchip,px30-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- clocks: A list of phandle + clock-specifier pairs for the clocks listed
|
||||
in clock-names
|
||||
- clock-names: Should contain the following:
|
||||
- "xin24m" for both PMUCRU and CRU
|
||||
- "gpll" for CRU (sourced from PMUCRU)
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing, pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "i2sx_clkin" - external I2S clock - optional,
|
||||
- "gmac_clkin" - external GMAC clock - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
pmucru: clock-controller@ff2bc000 {
|
||||
compatible = "rockchip,px30-pmucru";
|
||||
reg = <0x0 0xff2bc000 0x0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
cru: clock-controller@ff2b0000 {
|
||||
compatible = "rockchip,px30-cru";
|
||||
reg = <0x0 0xff2b0000 0x0 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@ff030000 {
|
||||
compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xff030000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,px30-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip PX30 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The PX30 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required
|
||||
- "xin32k" - rtc clock - optional
|
||||
- "i2sx_clkin" - external I2S clock - optional
|
||||
- "gmac_clkin" - external GMAC clock - optional
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,px30-cru
|
||||
- rockchip,px30-pmucru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Clock for both PMUCRU and CRU
|
||||
- description: Clock for CRU (sourced from PMUCRU)
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: xin24m
|
||||
- const: gpll
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: rockchip,px30-cru
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
maxItems: 1
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/px30-cru.h>
|
||||
|
||||
pmucru: clock-controller@ff2bc000 {
|
||||
compatible = "rockchip,px30-pmucru";
|
||||
reg = <0xff2bc000 0x1000>;
|
||||
clocks = <&xin24m>;
|
||||
clock-names = "xin24m";
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
cru: clock-controller@ff2b0000 {
|
||||
compatible = "rockchip,px30-cru";
|
||||
reg = <0xff2b0000 0x1000>;
|
||||
clocks = <&xin24m>, <&pmucru PLL_GPLL>;
|
||||
clock-names = "xin24m", "gpll";
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
* Rockchip RK3036 Clock and Reset Unit
|
||||
|
||||
The RK3036 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3036-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "ext_i2s" - external I2S clock - optional,
|
||||
- "rmii_clkin" - external EMAC clock - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: cru@20000000 {
|
||||
compatible = "rockchip,rk3036-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@20060000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x20060000 0x100>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3036-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RK3036 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RK3036 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required
|
||||
- "ext_i2s" - external I2S clock - optional
|
||||
- "rmii_clkin" - external EMAC clock - optional
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3036-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@20000000 {
|
||||
compatible = "rockchip,rk3036-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,61 +0,0 @@
|
|||
* Rockchip RK3188/RK3066 Clock and Reset Unit
|
||||
|
||||
The RK3188/RK3066 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
|
||||
"rockchip,rk3066a-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
|
||||
dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
|
||||
Similar macros exist for the reset sources in these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "xin27m" - 27mhz crystal input on rk3066 - optional,
|
||||
- "ext_hsadc" - external HSADC clock - optional,
|
||||
- "ext_cif0" - external camera clock - optional,
|
||||
- "ext_rmii" - external RMII clock - optional,
|
||||
- "ext_jtag" - externalJTAG clock - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: cru@20000000 {
|
||||
compatible = "rockchip,rk3188-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@10124000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x10124000 0x400>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3188-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RK3188/RK3066 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RK3188/RK3066 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
|
||||
dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
|
||||
Similar macros exist for the reset sources in these files.
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required
|
||||
- "xin32k" - RTC clock - optional
|
||||
- "xin27m" - 27mhz crystal input on RK3066 - optional
|
||||
- "ext_hsadc" - external HSADC clock - optional
|
||||
- "ext_cif0" - external camera clock - optional
|
||||
- "ext_rmii" - external RMII clock - optional
|
||||
- "ext_jtag" - external JTAG clock - optional
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3066a-cru
|
||||
- rockchip,rk3188-cru
|
||||
- rockchip,rk3188a-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@20000000 {
|
||||
compatible = "rockchip,rk3188-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,58 +0,0 @@
|
|||
* Rockchip RK3228 Clock and Reset Unit
|
||||
|
||||
The RK3228 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3228-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "ext_i2s" - external I2S clock - optional,
|
||||
- "ext_gmac" - external GMAC clock - optional
|
||||
- "ext_hsadc" - external HSADC clock - optional
|
||||
- "phy_50m_out" - output clock of the pll in the mac phy
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: cru@20000000 {
|
||||
compatible = "rockchip,rk3228-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@10110000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x10110000 0x100>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3228-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RK3228 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RK3228 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required
|
||||
- "ext_i2s" - external I2S clock - optional
|
||||
- "ext_gmac" - external GMAC clock - optional
|
||||
- "ext_hsadc" - external HSADC clock - optional
|
||||
- "phy_50m_out" - output clock of the pll in the mac phy
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3228-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@20000000 {
|
||||
compatible = "rockchip,rk3228-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,67 +0,0 @@
|
|||
* Rockchip RK3288 Clock and Reset Unit
|
||||
|
||||
The RK3288 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
A revision of this SoC is available: rk3288w. The clock tree is a bit
|
||||
different so another dt-compatible is available. Noticed that it is only
|
||||
setting the difference but there is no automatic revision detection. This
|
||||
should be performed by bootloaders.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3288-cru" or "rockchip,rk3288w-cru" in
|
||||
case of this revision of Rockchip rk3288.
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "ext_i2s" - external I2S clock - optional,
|
||||
- "ext_hsadc" - external HSADC clock - optional,
|
||||
- "ext_edp_24m" - external display port clock - optional,
|
||||
- "ext_vip" - external VIP clock - optional,
|
||||
- "ext_isp" - external ISP clock - optional,
|
||||
- "ext_jtag" - external JTAG clock - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: cru@20000000 {
|
||||
compatible = "rockchip,rk3188-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@10124000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x10124000 0x400>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3288-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RK3288 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RK3288 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
A revision of this SoC is available: rk3288w. The clock tree is a bit
|
||||
different so another dt-compatible is available. Noticed that it is only
|
||||
setting the difference but there is no automatic revision detection. This
|
||||
should be performed by boot loaders.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "ext_i2s" - external I2S clock - optional,
|
||||
- "ext_hsadc" - external HSADC clock - optional,
|
||||
- "ext_edp_24m" - external display port clock - optional,
|
||||
- "ext_vip" - external VIP clock - optional,
|
||||
- "ext_isp" - external ISP clock - optional,
|
||||
- "ext_jtag" - external JTAG clock - optional
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3288-cru
|
||||
- rockchip,rk3288w-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@ff760000 {
|
||||
compatible = "rockchip,rk3288-cru";
|
||||
reg = <0xff760000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,60 +0,0 @@
|
|||
* Rockchip RK3308 Clock and Reset Unit
|
||||
|
||||
The RK3308 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: CRU should be "rockchip,rk3308-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing, pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", "mclk_i2s2_8ch_in",
|
||||
"mclk_i2s3_8ch_in", "mclk_i2s0_2ch_in",
|
||||
"mclk_i2s1_2ch_in" - external I2S or SPDIF clock - optional,
|
||||
- "mac_clkin" - external MAC clock - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: clock-controller@ff500000 {
|
||||
compatible = "rockchip,rk3308-cru";
|
||||
reg = <0x0 0xff500000 0x0 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@ff0a0000 {
|
||||
compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xff0a0000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3308-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RK3308 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RK3308 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required
|
||||
- "xin32k" - rtc clock - optional
|
||||
- "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in",
|
||||
"mclk_i2s2_8ch_in", "mclk_i2s3_8ch_in",
|
||||
"mclk_i2s0_2ch_in", "mclk_i2s1_2ch_in" - external I2S or
|
||||
SPDIF clock - optional
|
||||
- "mac_clkin" - external MAC clock - optional
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3308-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@ff500000 {
|
||||
compatible = "rockchip,rk3308-cru";
|
||||
reg = <0xff500000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,61 +0,0 @@
|
|||
* Rockchip RK3368 Clock and Reset Unit
|
||||
|
||||
The RK3368 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3368-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing, pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "ext_i2s" - external I2S clock - optional,
|
||||
- "ext_gmac" - external GMAC clock - optional
|
||||
- "ext_hsadc" - external HSADC clock - optional,
|
||||
- "ext_isp" - external ISP clock - optional,
|
||||
- "ext_jtag" - external JTAG clock - optional
|
||||
- "ext_vip" - external VIP clock - optional,
|
||||
- "usbotg_out" - output clock of the pll in the otg phy
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: clock-controller@ff760000 {
|
||||
compatible = "rockchip,rk3368-cru";
|
||||
reg = <0x0 0xff760000 0x0 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@10124000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x10124000 0x400>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3368-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RK3368 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RK3368 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required
|
||||
- "xin32k" - rtc clock - optional
|
||||
- "ext_i2s" - external I2S clock - optional
|
||||
- "ext_gmac" - external GMAC clock - optional
|
||||
- "ext_hsadc" - external HSADC clock - optional
|
||||
- "ext_isp" - external ISP clock - optional
|
||||
- "ext_jtag" - external JTAG clock - optional
|
||||
- "ext_vip" - external VIP clock - optional
|
||||
- "usbotg_out" - output clock of the pll in the otg phy
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3368-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@ff760000 {
|
||||
compatible = "rockchip,rk3368-cru";
|
||||
reg = <0xff760000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Rockchip RK3399 Clock and Reset Unit
|
||||
|
||||
maintainers:
|
||||
- Xing Zheng <zhengxing@rock-chips.com>
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
|
|
@ -22,11 +22,11 @@ description: |
|
|||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "clkin_gmac" - external GMAC clock - optional,
|
||||
- "clkin_i2s" - external I2S clock - optional,
|
||||
- "pclkin_cif" - external ISP clock - optional,
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "clkin_gmac" - external GMAC clock - optional,
|
||||
- "clkin_i2s" - external I2S clock - optional,
|
||||
- "pclkin_cif" - external ISP clock - optional,
|
||||
- "clk_usbphy0_480m" - output clock of the pll in the usbphy0
|
||||
- "clk_usbphy1_480m" - output clock of the pll in the usbphy1
|
||||
|
||||
|
|
@ -46,24 +46,15 @@ properties:
|
|||
const: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 1
|
||||
|
||||
assigned-clocks:
|
||||
minItems: 1
|
||||
maxItems: 64
|
||||
|
||||
assigned-clock-parents:
|
||||
minItems: 1
|
||||
maxItems: 64
|
||||
|
||||
assigned-clock-rates:
|
||||
minItems: 1
|
||||
maxItems: 64
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: >
|
||||
phandle to the syscon managing the "general register files". It is used
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files". It is used
|
||||
for GRF muxes, if missing any muxes present in the GRF will not be
|
||||
available.
|
||||
|
||||
|
|
@ -77,7 +68,7 @@ additionalProperties: false
|
|||
|
||||
examples:
|
||||
- |
|
||||
pmucru: pmu-clock-controller@ff750000 {
|
||||
pmucru: clock-controller@ff750000 {
|
||||
compatible = "rockchip,rk3399-pmucru";
|
||||
reg = <0xff750000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -34,6 +34,19 @@ properties:
|
|||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -1,59 +0,0 @@
|
|||
* Rockchip RV1108 Clock and Reset Unit
|
||||
|
||||
The RV1108 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rv1108-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "ext_vip" - external VIP clock - optional
|
||||
- "ext_i2s" - external I2S clock - optional
|
||||
- "ext_gmac" - external GMAC clock - optional
|
||||
- "hdmiphy" - external clock input derived from HDMI PHY - optional
|
||||
- "usbphy" - external clock input derived from USB PHY - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: cru@20200000 {
|
||||
compatible = "rockchip,rv1108-cru";
|
||||
reg = <0x20200000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@10230000 {
|
||||
compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
|
||||
reg = <0x10230000 0x100>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rv1108-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RV1108 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RV1108 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required
|
||||
- "ext_vip" - external VIP clock - optional
|
||||
- "ext_i2s" - external I2S clock - optional
|
||||
- "ext_gmac" - external GMAC clock - optional
|
||||
- "hdmiphy" - external clock input derived from HDMI PHY - optional
|
||||
- "usbphy" - external clock input derived from USB PHY - optional
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rv1108-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@20200000 {
|
||||
compatible = "rockchip,rv1108-cru";
|
||||
reg = <0x20200000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,219 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,exynosautov9-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos Auto v9 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Chanho Park <chanho61.park@samsung.com>
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
description: |
|
||||
Exynos Auto v9 clock controller is comprised of several CMU units, generating
|
||||
clocks for different domains. Those CMU units are modeled as separate device
|
||||
tree nodes, and might depend on each other. Root clocks in that clock tree are
|
||||
two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
|
||||
The external OSCCLK must be defined as fixed-rate clock in dts.
|
||||
|
||||
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
|
||||
dividers; all other clocks of function blocks (other CMUs) are usually
|
||||
derived from CMU_TOP.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All clocks available for usage
|
||||
in clock consumer nodes are defined as preprocessor macros in
|
||||
'include/dt-bindings/clock/samsung,exynosautov9.h' header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynosautov9-cmu-top
|
||||
- samsung,exynosautov9-cmu-busmc
|
||||
- samsung,exynosautov9-cmu-core
|
||||
- samsung,exynosautov9-cmu-fsys2
|
||||
- samsung,exynosautov9-cmu-peric0
|
||||
- samsung,exynosautov9-cmu-peric1
|
||||
- samsung,exynosautov9-cmu-peris
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov9-cmu-top
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov9-cmu-busmc
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_BUSMC bus clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_clkcmu_busmc_bus
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov9-cmu-core
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_CORE bus clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_clkcmu_core_bus
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov9-cmu-fsys2
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_FSYS2 bus clock (from CMU_TOP)
|
||||
- description: UFS clock (from CMU_TOP)
|
||||
- description: Ethernet clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_clkcmu_fsys2_bus
|
||||
- const: dout_fsys2_clkcmu_ufs_embd
|
||||
- const: dout_fsys2_clkcmu_ethernet
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov9-cmu-peric0
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_PERIC0 bus clock (from CMU_TOP)
|
||||
- description: PERIC0 IP clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_clkcmu_peric0_bus
|
||||
- const: dout_clkcmu_peric0_ip
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov9-cmu-peric1
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_PERIC1 bus clock (from CMU_TOP)
|
||||
- description: PERIC1 IP clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_clkcmu_peric1_bus
|
||||
- const: dout_clkcmu_peric1_ip
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynosautov9-cmu-peris
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_PERIS bus clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_clkcmu_peris_bus
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock controller node for CMU_FSYS2
|
||||
- |
|
||||
#include <dt-bindings/clock/samsung,exynosautov9.h>
|
||||
|
||||
cmu_fsys2: clock-controller@17c00000 {
|
||||
compatible = "samsung,exynosautov9-cmu-fsys2";
|
||||
reg = <0x17c00000 0x8000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&xtcxo>,
|
||||
<&cmu_top DOUT_CLKCMU_FSYS2_BUS>,
|
||||
<&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>,
|
||||
<&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>;
|
||||
clock-names = "oscclk",
|
||||
"dout_clkcmu_fsys2_bus",
|
||||
"dout_fsys2_clkcmu_ufs_embd",
|
||||
"dout_fsys2_clkcmu_ethernet";
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -41,6 +41,7 @@ description: |
|
|||
|
||||
The list of valid indices for STM32MP1 is available in:
|
||||
include/dt-bindings/reset-controller/stm32mp1-resets.h
|
||||
include/dt-bindings/reset-controller/stm32mp13-resets.h
|
||||
|
||||
This file implements defines like:
|
||||
#define LTDC_R 3072
|
||||
|
|
@ -57,6 +58,7 @@ properties:
|
|||
- enum:
|
||||
- st,stm32mp1-rcc-secure
|
||||
- st,stm32mp1-rcc
|
||||
- st,stm32mp13-rcc
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
|
|
|
|||
|
|
@ -131,36 +131,10 @@ static const struct platform_suspend_ops ingenic_pm_ops __maybe_unused = {
|
|||
|
||||
static int __init ingenic_pm_init(void)
|
||||
{
|
||||
struct device_node *cpu_node;
|
||||
struct clk *cpu0_clk;
|
||||
int ret;
|
||||
|
||||
if (boot_cpu_type() == CPU_XBURST) {
|
||||
if (IS_ENABLED(CONFIG_PM_SLEEP))
|
||||
suspend_set_ops(&ingenic_pm_ops);
|
||||
_machine_halt = ingenic_halt;
|
||||
|
||||
/*
|
||||
* Unconditionally enable the clock for the first CPU.
|
||||
* This makes sure that the PLL that feeds the CPU won't be
|
||||
* stopped while the kernel is running.
|
||||
*/
|
||||
cpu_node = of_get_cpu_node(0, NULL);
|
||||
if (!cpu_node) {
|
||||
pr_err("Unable to get CPU node\n");
|
||||
} else {
|
||||
cpu0_clk = of_clk_get(cpu_node, 0);
|
||||
if (IS_ERR(cpu0_clk)) {
|
||||
pr_err("Unable to get CPU0 clock\n");
|
||||
return PTR_ERR(cpu0_clk);
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(cpu0_clk);
|
||||
if (ret) {
|
||||
pr_err("Unable to enable CPU0 clock\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -377,6 +377,11 @@ config COMMON_CLK_VC5
|
|||
This driver supports the IDT VersaClock 5 and VersaClock 6
|
||||
programmable clock generators.
|
||||
|
||||
config COMMON_CLK_STM32MP135
|
||||
def_bool COMMON_CLK && MACH_STM32MP13
|
||||
help
|
||||
Support for stm32mp135 SoC family clocks
|
||||
|
||||
config COMMON_CLK_STM32MP157
|
||||
def_bool COMMON_CLK && MACH_STM32MP157
|
||||
help
|
||||
|
|
|
|||
|
|
@ -116,6 +116,7 @@ obj-y += socfpga/
|
|||
obj-$(CONFIG_PLAT_SPEAR) += spear/
|
||||
obj-y += sprd/
|
||||
obj-$(CONFIG_ARCH_STI) += st/
|
||||
obj-$(CONFIG_ARCH_STM32) += stm32/
|
||||
obj-$(CONFIG_SOC_STARFIVE) += starfive/
|
||||
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
|
||||
obj-y += sunxi-ng/
|
||||
|
|
|
|||
|
|
@ -660,7 +660,7 @@ static int ingenic_register_clock(struct ingenic_cgu *cgu, unsigned idx)
|
|||
ingenic_clk->idx = idx;
|
||||
|
||||
clk_init.name = clk_info->name;
|
||||
clk_init.flags = 0;
|
||||
clk_init.flags = clk_info->flags;
|
||||
clk_init.parent_names = parent_names;
|
||||
|
||||
caps = clk_info->type;
|
||||
|
|
|
|||
|
|
@ -136,6 +136,7 @@ struct ingenic_cgu_custom_info {
|
|||
* struct ingenic_cgu_clk_info - information about a clock
|
||||
* @name: name of the clock
|
||||
* @type: a bitmask formed from CGU_CLK_* values
|
||||
* @flags: common clock flags to set on this clock
|
||||
* @parents: an array of the indices of potential parents of this clock
|
||||
* within the clock_info array of the CGU, or -1 in entries
|
||||
* which correspond to no valid parent
|
||||
|
|
@ -161,6 +162,8 @@ struct ingenic_cgu_clk_info {
|
|||
CGU_CLK_CUSTOM = BIT(7),
|
||||
} type;
|
||||
|
||||
unsigned long flags;
|
||||
|
||||
int parents[4];
|
||||
|
||||
union {
|
||||
|
|
|
|||
|
|
@ -87,6 +87,11 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
|
|||
|
||||
[JZ4725B_CLK_CCLK] = {
|
||||
"cclk", CGU_CLK_DIV,
|
||||
/*
|
||||
* Disabling the CPU clock or any parent clocks will hang the
|
||||
* system; mark it critical.
|
||||
*/
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
|
||||
.div = {
|
||||
CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
|
||||
|
|
@ -114,6 +119,11 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
|
|||
|
||||
[JZ4725B_CLK_MCLK] = {
|
||||
"mclk", CGU_CLK_DIV,
|
||||
/*
|
||||
* Disabling MCLK or its parents will render DRAM
|
||||
* inaccessible; mark it critical.
|
||||
*/
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
|
||||
.div = {
|
||||
CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
|
||||
|
|
|
|||
|
|
@ -102,6 +102,11 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
|
|||
|
||||
[JZ4740_CLK_CCLK] = {
|
||||
"cclk", CGU_CLK_DIV,
|
||||
/*
|
||||
* Disabling the CPU clock or any parent clocks will hang the
|
||||
* system; mark it critical.
|
||||
*/
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
|
||||
.div = {
|
||||
CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
|
||||
|
|
@ -129,6 +134,11 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
|
|||
|
||||
[JZ4740_CLK_MCLK] = {
|
||||
"mclk", CGU_CLK_DIV,
|
||||
/*
|
||||
* Disabling MCLK or its parents will render DRAM
|
||||
* inaccessible; mark it critical.
|
||||
*/
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
|
||||
.div = {
|
||||
CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
|
||||
|
|
|
|||
|
|
@ -143,6 +143,11 @@ static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = {
|
|||
|
||||
[JZ4760_CLK_CCLK] = {
|
||||
"cclk", CGU_CLK_DIV,
|
||||
/*
|
||||
* Disabling the CPU clock or any parent clocks will hang the
|
||||
* system; mark it critical.
|
||||
*/
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
.parents = { JZ4760_CLK_PLL0, },
|
||||
.div = {
|
||||
CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
|
||||
|
|
@ -175,6 +180,11 @@ static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = {
|
|||
},
|
||||
[JZ4760_CLK_MCLK] = {
|
||||
"mclk", CGU_CLK_DIV,
|
||||
/*
|
||||
* Disabling MCLK or its parents will render DRAM
|
||||
* inaccessible; mark it critical.
|
||||
*/
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
.parents = { JZ4760_CLK_PLL0, },
|
||||
.div = {
|
||||
CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
|
||||
|
|
|
|||
|
|
@ -149,6 +149,11 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
|
|||
|
||||
[JZ4770_CLK_CCLK] = {
|
||||
"cclk", CGU_CLK_DIV,
|
||||
/*
|
||||
* Disabling the CPU clock or any parent clocks will hang the
|
||||
* system; mark it critical.
|
||||
*/
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
.parents = { JZ4770_CLK_PLL0, },
|
||||
.div = {
|
||||
CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
|
||||
|
|
|
|||
|
|
@ -341,12 +341,22 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
|
|||
|
||||
[JZ4780_CLK_CPU] = {
|
||||
"cpu", CGU_CLK_DIV,
|
||||
/*
|
||||
* Disabling the CPU clock or any parent clocks will hang the
|
||||
* system; mark it critical.
|
||||
*/
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
.parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
|
||||
.div = { CGU_REG_CLOCKCONTROL, 0, 1, 4, 22, -1, -1 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_L2CACHE] = {
|
||||
"l2cache", CGU_CLK_DIV,
|
||||
/*
|
||||
* The L2 cache clock is critical if caches are enabled and
|
||||
* disabling it or any parent clocks will hang the system.
|
||||
*/
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
.parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
|
||||
.div = { CGU_REG_CLOCKCONTROL, 4, 1, 4, -1, -1, -1 },
|
||||
},
|
||||
|
|
@ -380,6 +390,11 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
|
|||
|
||||
[JZ4780_CLK_DDR] = {
|
||||
"ddr", CGU_CLK_MUX | CGU_CLK_DIV,
|
||||
/*
|
||||
* Disabling DDR clock or its parents will render DRAM
|
||||
* inaccessible; mark it critical.
|
||||
*/
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
.parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },
|
||||
.mux = { CGU_REG_DDRCDR, 30, 2 },
|
||||
.div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@ struct ingenic_soc_info {
|
|||
unsigned int num_channels;
|
||||
bool has_ost;
|
||||
bool has_tcu_clk;
|
||||
bool allow_missing_tcu_clk;
|
||||
};
|
||||
|
||||
struct ingenic_tcu_clk_info {
|
||||
|
|
@ -320,7 +321,8 @@ static const struct ingenic_soc_info jz4770_soc_info = {
|
|||
static const struct ingenic_soc_info x1000_soc_info = {
|
||||
.num_channels = 8,
|
||||
.has_ost = false, /* X1000 has OST, but it not belong TCU */
|
||||
.has_tcu_clk = false,
|
||||
.has_tcu_clk = true,
|
||||
.allow_missing_tcu_clk = true,
|
||||
};
|
||||
|
||||
static const struct of_device_id __maybe_unused ingenic_tcu_of_match[] __initconst = {
|
||||
|
|
@ -355,14 +357,27 @@ static int __init ingenic_tcu_probe(struct device_node *np)
|
|||
tcu->clk = of_clk_get_by_name(np, "tcu");
|
||||
if (IS_ERR(tcu->clk)) {
|
||||
ret = PTR_ERR(tcu->clk);
|
||||
pr_crit("Cannot get TCU clock\n");
|
||||
goto err_free_tcu;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(tcu->clk);
|
||||
if (ret) {
|
||||
pr_crit("Unable to enable TCU clock\n");
|
||||
goto err_put_clk;
|
||||
/*
|
||||
* Old device trees for some SoCs did not include the
|
||||
* TCU clock because this driver (incorrectly) didn't
|
||||
* use it. In this case we complain loudly and attempt
|
||||
* to continue without the clock, which might work if
|
||||
* booting with workarounds like "clk_ignore_unused".
|
||||
*/
|
||||
if (tcu->soc_info->allow_missing_tcu_clk && ret == -EINVAL) {
|
||||
pr_warn("TCU clock missing from device tree, please update your device tree\n");
|
||||
tcu->clk = NULL;
|
||||
} else {
|
||||
pr_crit("Cannot get TCU clock from device tree\n");
|
||||
goto err_free_tcu;
|
||||
}
|
||||
} else {
|
||||
ret = clk_prepare_enable(tcu->clk);
|
||||
if (ret) {
|
||||
pr_crit("Unable to enable TCU clock\n");
|
||||
goto err_put_clk;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -432,10 +447,10 @@ static int __init ingenic_tcu_probe(struct device_node *np)
|
|||
clk_hw_unregister(tcu->clocks->hws[i]);
|
||||
kfree(tcu->clocks);
|
||||
err_clk_disable:
|
||||
if (tcu->soc_info->has_tcu_clk)
|
||||
if (tcu->clk)
|
||||
clk_disable_unprepare(tcu->clk);
|
||||
err_put_clk:
|
||||
if (tcu->soc_info->has_tcu_clk)
|
||||
if (tcu->clk)
|
||||
clk_put(tcu->clk);
|
||||
err_free_tcu:
|
||||
kfree(tcu);
|
||||
|
|
|
|||
|
|
@ -251,6 +251,11 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
|
|||
|
||||
[X1000_CLK_CPU] = {
|
||||
"cpu", CGU_CLK_DIV | CGU_CLK_GATE,
|
||||
/*
|
||||
* Disabling the CPU clock or any parent clocks will hang the
|
||||
* system; mark it critical.
|
||||
*/
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
.parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
|
||||
.div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR, 30 },
|
||||
|
|
@ -258,6 +263,11 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
|
|||
|
||||
[X1000_CLK_L2CACHE] = {
|
||||
"l2cache", CGU_CLK_DIV,
|
||||
/*
|
||||
* The L2 cache clock is critical if caches are enabled and
|
||||
* disabling it or any parent clocks will hang the system.
|
||||
*/
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
.parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
|
||||
.div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
|
||||
},
|
||||
|
|
@ -290,6 +300,11 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
|
|||
|
||||
[X1000_CLK_DDR] = {
|
||||
"ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
|
||||
/*
|
||||
* Disabling DDR clock or its parents will render DRAM
|
||||
* inaccessible; mark it critical.
|
||||
*/
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
|
||||
.mux = { CGU_REG_DDRCDR, 30, 2 },
|
||||
.div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },
|
||||
|
|
|
|||
|
|
@ -225,6 +225,7 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = {
|
|||
|
||||
[X1830_CLK_CPU] = {
|
||||
"cpu", CGU_CLK_DIV | CGU_CLK_GATE,
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
.parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
|
||||
.div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR1, 15 },
|
||||
|
|
@ -232,6 +233,11 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = {
|
|||
|
||||
[X1830_CLK_L2CACHE] = {
|
||||
"l2cache", CGU_CLK_DIV,
|
||||
/*
|
||||
* The L2 cache clock is critical if caches are enabled and
|
||||
* disabling it or any parent clocks will hang the system.
|
||||
*/
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
.parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
|
||||
.div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
|
||||
},
|
||||
|
|
@ -264,6 +270,11 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = {
|
|||
|
||||
[X1830_CLK_DDR] = {
|
||||
"ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
|
||||
/*
|
||||
* Disabling DDR clock or its parents will render DRAM
|
||||
* inaccessible; mark it critical.
|
||||
*/
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
.parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
|
||||
.mux = { CGU_REG_DDRCDR, 30, 2 },
|
||||
.div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },
|
||||
|
|
|
|||
|
|
@ -1591,6 +1591,7 @@ static const char *const rk3568_cru_critical_clocks[] __initconst = {
|
|||
"hclk_php",
|
||||
"pclk_php",
|
||||
"hclk_usb",
|
||||
"hclk_vo",
|
||||
};
|
||||
|
||||
static const char *const rk3568_pmucru_critical_clocks[] __initconst = {
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos-arm64.o
|
|||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o
|
||||
obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
|
||||
obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
|
||||
obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1 @@
|
|||
obj-$(CONFIG_COMMON_CLK_STM32MP135) += clk-stm32mp13.o clk-stm32-core.o reset-stm32.o
|
||||
|
|
@ -0,0 +1,695 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
|
||||
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include "clk-stm32-core.h"
|
||||
#include "reset-stm32.h"
|
||||
|
||||
static DEFINE_SPINLOCK(rlock);
|
||||
|
||||
static int stm32_rcc_clock_init(struct device *dev,
|
||||
const struct of_device_id *match,
|
||||
void __iomem *base)
|
||||
{
|
||||
const struct stm32_rcc_match_data *data = match->data;
|
||||
struct clk_hw_onecell_data *clk_data = data->hw_clks;
|
||||
struct device_node *np = dev_of_node(dev);
|
||||
struct clk_hw **hws;
|
||||
int n, max_binding;
|
||||
|
||||
max_binding = data->maxbinding;
|
||||
|
||||
clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, max_binding), GFP_KERNEL);
|
||||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
|
||||
clk_data->num = max_binding;
|
||||
|
||||
hws = clk_data->hws;
|
||||
|
||||
for (n = 0; n < max_binding; n++)
|
||||
hws[n] = ERR_PTR(-ENOENT);
|
||||
|
||||
for (n = 0; n < data->num_clocks; n++) {
|
||||
const struct clock_config *cfg_clock = &data->tab_clocks[n];
|
||||
struct clk_hw *hw = ERR_PTR(-ENOENT);
|
||||
|
||||
if (data->check_security &&
|
||||
data->check_security(base, cfg_clock))
|
||||
continue;
|
||||
|
||||
if (cfg_clock->func)
|
||||
hw = (*cfg_clock->func)(dev, data, base, &rlock,
|
||||
cfg_clock);
|
||||
|
||||
if (IS_ERR(hw)) {
|
||||
dev_err(dev, "Can't register clk %d: %ld\n", n,
|
||||
PTR_ERR(hw));
|
||||
return PTR_ERR(hw);
|
||||
}
|
||||
|
||||
if (cfg_clock->id != NO_ID)
|
||||
hws[cfg_clock->id] = hw;
|
||||
}
|
||||
|
||||
return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data,
|
||||
void __iomem *base)
|
||||
{
|
||||
const struct of_device_id *match;
|
||||
int err;
|
||||
|
||||
match = of_match_node(match_data, dev_of_node(dev));
|
||||
if (!match) {
|
||||
dev_err(dev, "match data not found\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* RCC Reset Configuration */
|
||||
err = stm32_rcc_reset_init(dev, match, base);
|
||||
if (err) {
|
||||
pr_err("stm32 reset failed to initialize\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
/* RCC Clock Configuration */
|
||||
err = stm32_rcc_clock_init(dev, match, base);
|
||||
if (err) {
|
||||
pr_err("stm32 clock failed to initialize\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u8 stm32_mux_get_parent(void __iomem *base,
|
||||
struct clk_stm32_clock_data *data,
|
||||
u16 mux_id)
|
||||
{
|
||||
const struct stm32_mux_cfg *mux = &data->muxes[mux_id];
|
||||
u32 mask = BIT(mux->width) - 1;
|
||||
u32 val;
|
||||
|
||||
val = readl(base + mux->offset) >> mux->shift;
|
||||
val &= mask;
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static int stm32_mux_set_parent(void __iomem *base,
|
||||
struct clk_stm32_clock_data *data,
|
||||
u16 mux_id, u8 index)
|
||||
{
|
||||
const struct stm32_mux_cfg *mux = &data->muxes[mux_id];
|
||||
|
||||
u32 mask = BIT(mux->width) - 1;
|
||||
u32 reg = readl(base + mux->offset);
|
||||
u32 val = index << mux->shift;
|
||||
|
||||
reg &= ~(mask << mux->shift);
|
||||
reg |= val;
|
||||
|
||||
writel(reg, base + mux->offset);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void stm32_gate_endisable(void __iomem *base,
|
||||
struct clk_stm32_clock_data *data,
|
||||
u16 gate_id, int enable)
|
||||
{
|
||||
const struct stm32_gate_cfg *gate = &data->gates[gate_id];
|
||||
void __iomem *addr = base + gate->offset;
|
||||
|
||||
if (enable) {
|
||||
if (data->gate_cpt[gate_id]++ > 0)
|
||||
return;
|
||||
|
||||
if (gate->set_clr != 0)
|
||||
writel(BIT(gate->bit_idx), addr);
|
||||
else
|
||||
writel(readl(addr) | BIT(gate->bit_idx), addr);
|
||||
} else {
|
||||
if (--data->gate_cpt[gate_id] > 0)
|
||||
return;
|
||||
|
||||
if (gate->set_clr != 0)
|
||||
writel(BIT(gate->bit_idx), addr + gate->set_clr);
|
||||
else
|
||||
writel(readl(addr) & ~BIT(gate->bit_idx), addr);
|
||||
}
|
||||
}
|
||||
|
||||
static void stm32_gate_disable_unused(void __iomem *base,
|
||||
struct clk_stm32_clock_data *data,
|
||||
u16 gate_id)
|
||||
{
|
||||
const struct stm32_gate_cfg *gate = &data->gates[gate_id];
|
||||
void __iomem *addr = base + gate->offset;
|
||||
|
||||
if (data->gate_cpt[gate_id] > 0)
|
||||
return;
|
||||
|
||||
if (gate->set_clr != 0)
|
||||
writel(BIT(gate->bit_idx), addr + gate->set_clr);
|
||||
else
|
||||
writel(readl(addr) & ~BIT(gate->bit_idx), addr);
|
||||
}
|
||||
|
||||
static int stm32_gate_is_enabled(void __iomem *base,
|
||||
struct clk_stm32_clock_data *data,
|
||||
u16 gate_id)
|
||||
{
|
||||
const struct stm32_gate_cfg *gate = &data->gates[gate_id];
|
||||
|
||||
return (readl(base + gate->offset) & BIT(gate->bit_idx)) != 0;
|
||||
}
|
||||
|
||||
static unsigned int _get_table_div(const struct clk_div_table *table,
|
||||
unsigned int val)
|
||||
{
|
||||
const struct clk_div_table *clkt;
|
||||
|
||||
for (clkt = table; clkt->div; clkt++)
|
||||
if (clkt->val == val)
|
||||
return clkt->div;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned int _get_div(const struct clk_div_table *table,
|
||||
unsigned int val, unsigned long flags, u8 width)
|
||||
{
|
||||
if (flags & CLK_DIVIDER_ONE_BASED)
|
||||
return val;
|
||||
if (flags & CLK_DIVIDER_POWER_OF_TWO)
|
||||
return 1 << val;
|
||||
if (table)
|
||||
return _get_table_div(table, val);
|
||||
return val + 1;
|
||||
}
|
||||
|
||||
static unsigned long stm32_divider_get_rate(void __iomem *base,
|
||||
struct clk_stm32_clock_data *data,
|
||||
u16 div_id,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
const struct stm32_div_cfg *divider = &data->dividers[div_id];
|
||||
unsigned int val;
|
||||
unsigned int div;
|
||||
|
||||
val = readl(base + divider->offset) >> divider->shift;
|
||||
val &= clk_div_mask(divider->width);
|
||||
div = _get_div(divider->table, val, divider->flags, divider->width);
|
||||
|
||||
if (!div) {
|
||||
WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
|
||||
"%d: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
|
||||
div_id);
|
||||
return parent_rate;
|
||||
}
|
||||
|
||||
return DIV_ROUND_UP_ULL((u64)parent_rate, div);
|
||||
}
|
||||
|
||||
static int stm32_divider_set_rate(void __iomem *base,
|
||||
struct clk_stm32_clock_data *data,
|
||||
u16 div_id, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
const struct stm32_div_cfg *divider = &data->dividers[div_id];
|
||||
int value;
|
||||
u32 val;
|
||||
|
||||
value = divider_get_val(rate, parent_rate, divider->table,
|
||||
divider->width, divider->flags);
|
||||
if (value < 0)
|
||||
return value;
|
||||
|
||||
if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
|
||||
val = clk_div_mask(divider->width) << (divider->shift + 16);
|
||||
} else {
|
||||
val = readl(base + divider->offset);
|
||||
val &= ~(clk_div_mask(divider->width) << divider->shift);
|
||||
}
|
||||
|
||||
val |= (u32)value << divider->shift;
|
||||
|
||||
writel(val, base + divider->offset);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u8 clk_stm32_mux_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_stm32_mux *mux = to_clk_stm32_mux(hw);
|
||||
|
||||
return stm32_mux_get_parent(mux->base, mux->clock_data, mux->mux_id);
|
||||
}
|
||||
|
||||
static int clk_stm32_mux_set_parent(struct clk_hw *hw, u8 index)
|
||||
{
|
||||
struct clk_stm32_mux *mux = to_clk_stm32_mux(hw);
|
||||
unsigned long flags = 0;
|
||||
|
||||
spin_lock_irqsave(mux->lock, flags);
|
||||
|
||||
stm32_mux_set_parent(mux->base, mux->clock_data, mux->mux_id, index);
|
||||
|
||||
spin_unlock_irqrestore(mux->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct clk_ops clk_stm32_mux_ops = {
|
||||
.get_parent = clk_stm32_mux_get_parent,
|
||||
.set_parent = clk_stm32_mux_set_parent,
|
||||
};
|
||||
|
||||
static void clk_stm32_gate_endisable(struct clk_hw *hw, int enable)
|
||||
{
|
||||
struct clk_stm32_gate *gate = to_clk_stm32_gate(hw);
|
||||
unsigned long flags = 0;
|
||||
|
||||
spin_lock_irqsave(gate->lock, flags);
|
||||
|
||||
stm32_gate_endisable(gate->base, gate->clock_data, gate->gate_id, enable);
|
||||
|
||||
spin_unlock_irqrestore(gate->lock, flags);
|
||||
}
|
||||
|
||||
static int clk_stm32_gate_enable(struct clk_hw *hw)
|
||||
{
|
||||
clk_stm32_gate_endisable(hw, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void clk_stm32_gate_disable(struct clk_hw *hw)
|
||||
{
|
||||
clk_stm32_gate_endisable(hw, 0);
|
||||
}
|
||||
|
||||
static int clk_stm32_gate_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_stm32_gate *gate = to_clk_stm32_gate(hw);
|
||||
|
||||
return stm32_gate_is_enabled(gate->base, gate->clock_data, gate->gate_id);
|
||||
}
|
||||
|
||||
static void clk_stm32_gate_disable_unused(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_stm32_gate *gate = to_clk_stm32_gate(hw);
|
||||
unsigned long flags = 0;
|
||||
|
||||
spin_lock_irqsave(gate->lock, flags);
|
||||
|
||||
stm32_gate_disable_unused(gate->base, gate->clock_data, gate->gate_id);
|
||||
|
||||
spin_unlock_irqrestore(gate->lock, flags);
|
||||
}
|
||||
|
||||
const struct clk_ops clk_stm32_gate_ops = {
|
||||
.enable = clk_stm32_gate_enable,
|
||||
.disable = clk_stm32_gate_disable,
|
||||
.is_enabled = clk_stm32_gate_is_enabled,
|
||||
.disable_unused = clk_stm32_gate_disable_unused,
|
||||
};
|
||||
|
||||
static int clk_stm32_divider_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_stm32_div *div = to_clk_stm32_divider(hw);
|
||||
unsigned long flags = 0;
|
||||
int ret;
|
||||
|
||||
if (div->div_id == NO_STM32_DIV)
|
||||
return rate;
|
||||
|
||||
spin_lock_irqsave(div->lock, flags);
|
||||
|
||||
ret = stm32_divider_set_rate(div->base, div->clock_data, div->div_id, rate, parent_rate);
|
||||
|
||||
spin_unlock_irqrestore(div->lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static long clk_stm32_divider_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
struct clk_stm32_div *div = to_clk_stm32_divider(hw);
|
||||
const struct stm32_div_cfg *divider;
|
||||
|
||||
if (div->div_id == NO_STM32_DIV)
|
||||
return rate;
|
||||
|
||||
divider = &div->clock_data->dividers[div->div_id];
|
||||
|
||||
/* if read only, just return current value */
|
||||
if (divider->flags & CLK_DIVIDER_READ_ONLY) {
|
||||
u32 val;
|
||||
|
||||
val = readl(div->base + divider->offset) >> divider->shift;
|
||||
val &= clk_div_mask(divider->width);
|
||||
|
||||
return divider_ro_round_rate(hw, rate, prate, divider->table,
|
||||
divider->width, divider->flags,
|
||||
val);
|
||||
}
|
||||
|
||||
return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
|
||||
rate, prate, divider->table,
|
||||
divider->width, divider->flags);
|
||||
}
|
||||
|
||||
static unsigned long clk_stm32_divider_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_stm32_div *div = to_clk_stm32_divider(hw);
|
||||
|
||||
if (div->div_id == NO_STM32_DIV)
|
||||
return parent_rate;
|
||||
|
||||
return stm32_divider_get_rate(div->base, div->clock_data, div->div_id, parent_rate);
|
||||
}
|
||||
|
||||
const struct clk_ops clk_stm32_divider_ops = {
|
||||
.recalc_rate = clk_stm32_divider_recalc_rate,
|
||||
.round_rate = clk_stm32_divider_round_rate,
|
||||
.set_rate = clk_stm32_divider_set_rate,
|
||||
};
|
||||
|
||||
static int clk_stm32_composite_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
|
||||
unsigned long flags = 0;
|
||||
int ret;
|
||||
|
||||
if (composite->div_id == NO_STM32_DIV)
|
||||
return rate;
|
||||
|
||||
spin_lock_irqsave(composite->lock, flags);
|
||||
|
||||
ret = stm32_divider_set_rate(composite->base, composite->clock_data,
|
||||
composite->div_id, rate, parent_rate);
|
||||
|
||||
spin_unlock_irqrestore(composite->lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static unsigned long clk_stm32_composite_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
|
||||
|
||||
if (composite->div_id == NO_STM32_DIV)
|
||||
return parent_rate;
|
||||
|
||||
return stm32_divider_get_rate(composite->base, composite->clock_data,
|
||||
composite->div_id, parent_rate);
|
||||
}
|
||||
|
||||
static long clk_stm32_composite_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
|
||||
|
||||
const struct stm32_div_cfg *divider;
|
||||
|
||||
if (composite->div_id == NO_STM32_DIV)
|
||||
return rate;
|
||||
|
||||
divider = &composite->clock_data->dividers[composite->div_id];
|
||||
|
||||
/* if read only, just return current value */
|
||||
if (divider->flags & CLK_DIVIDER_READ_ONLY) {
|
||||
u32 val;
|
||||
|
||||
val = readl(composite->base + divider->offset) >> divider->shift;
|
||||
val &= clk_div_mask(divider->width);
|
||||
|
||||
return divider_ro_round_rate(hw, rate, prate, divider->table,
|
||||
divider->width, divider->flags,
|
||||
val);
|
||||
}
|
||||
|
||||
return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
|
||||
rate, prate, divider->table,
|
||||
divider->width, divider->flags);
|
||||
}
|
||||
|
||||
static u8 clk_stm32_composite_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
|
||||
|
||||
return stm32_mux_get_parent(composite->base, composite->clock_data, composite->mux_id);
|
||||
}
|
||||
|
||||
static int clk_stm32_composite_set_parent(struct clk_hw *hw, u8 index)
|
||||
{
|
||||
struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
|
||||
unsigned long flags = 0;
|
||||
|
||||
spin_lock_irqsave(composite->lock, flags);
|
||||
|
||||
stm32_mux_set_parent(composite->base, composite->clock_data, composite->mux_id, index);
|
||||
|
||||
spin_unlock_irqrestore(composite->lock, flags);
|
||||
|
||||
if (composite->clock_data->is_multi_mux) {
|
||||
struct clk_hw *other_mux_hw = composite->clock_data->is_multi_mux(hw);
|
||||
|
||||
if (other_mux_hw) {
|
||||
struct clk_hw *hwp = clk_hw_get_parent_by_index(hw, index);
|
||||
|
||||
clk_hw_reparent(other_mux_hw, hwp);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int clk_stm32_composite_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
|
||||
|
||||
if (composite->gate_id == NO_STM32_GATE)
|
||||
return (__clk_get_enable_count(hw->clk) > 0);
|
||||
|
||||
return stm32_gate_is_enabled(composite->base, composite->clock_data, composite->gate_id);
|
||||
}
|
||||
|
||||
#define MUX_SAFE_POSITION 0
|
||||
|
||||
static int clk_stm32_has_safe_mux(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
|
||||
const struct stm32_mux_cfg *mux = &composite->clock_data->muxes[composite->mux_id];
|
||||
|
||||
return !!(mux->flags & MUX_SAFE);
|
||||
}
|
||||
|
||||
static void clk_stm32_set_safe_position_mux(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
|
||||
|
||||
if (!clk_stm32_composite_is_enabled(hw)) {
|
||||
unsigned long flags = 0;
|
||||
|
||||
if (composite->clock_data->is_multi_mux) {
|
||||
struct clk_hw *other_mux_hw = NULL;
|
||||
|
||||
other_mux_hw = composite->clock_data->is_multi_mux(hw);
|
||||
|
||||
if (!other_mux_hw || clk_stm32_composite_is_enabled(other_mux_hw))
|
||||
return;
|
||||
}
|
||||
|
||||
spin_lock_irqsave(composite->lock, flags);
|
||||
|
||||
stm32_mux_set_parent(composite->base, composite->clock_data,
|
||||
composite->mux_id, MUX_SAFE_POSITION);
|
||||
|
||||
spin_unlock_irqrestore(composite->lock, flags);
|
||||
}
|
||||
}
|
||||
|
||||
static void clk_stm32_safe_restore_position_mux(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
|
||||
int sel = clk_hw_get_parent_index(hw);
|
||||
unsigned long flags = 0;
|
||||
|
||||
spin_lock_irqsave(composite->lock, flags);
|
||||
|
||||
stm32_mux_set_parent(composite->base, composite->clock_data, composite->mux_id, sel);
|
||||
|
||||
spin_unlock_irqrestore(composite->lock, flags);
|
||||
}
|
||||
|
||||
static void clk_stm32_composite_gate_endisable(struct clk_hw *hw, int enable)
|
||||
{
|
||||
struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
|
||||
unsigned long flags = 0;
|
||||
|
||||
spin_lock_irqsave(composite->lock, flags);
|
||||
|
||||
stm32_gate_endisable(composite->base, composite->clock_data, composite->gate_id, enable);
|
||||
|
||||
spin_unlock_irqrestore(composite->lock, flags);
|
||||
}
|
||||
|
||||
static int clk_stm32_composite_gate_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
|
||||
|
||||
if (composite->gate_id == NO_STM32_GATE)
|
||||
return 0;
|
||||
|
||||
clk_stm32_composite_gate_endisable(hw, 1);
|
||||
|
||||
if (composite->mux_id != NO_STM32_MUX && clk_stm32_has_safe_mux(hw))
|
||||
clk_stm32_safe_restore_position_mux(hw);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void clk_stm32_composite_gate_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
|
||||
|
||||
if (composite->gate_id == NO_STM32_GATE)
|
||||
return;
|
||||
|
||||
clk_stm32_composite_gate_endisable(hw, 0);
|
||||
|
||||
if (composite->mux_id != NO_STM32_MUX && clk_stm32_has_safe_mux(hw))
|
||||
clk_stm32_set_safe_position_mux(hw);
|
||||
}
|
||||
|
||||
static void clk_stm32_composite_disable_unused(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
|
||||
unsigned long flags = 0;
|
||||
|
||||
if (composite->gate_id == NO_STM32_GATE)
|
||||
return;
|
||||
|
||||
spin_lock_irqsave(composite->lock, flags);
|
||||
|
||||
stm32_gate_disable_unused(composite->base, composite->clock_data, composite->gate_id);
|
||||
|
||||
spin_unlock_irqrestore(composite->lock, flags);
|
||||
}
|
||||
|
||||
const struct clk_ops clk_stm32_composite_ops = {
|
||||
.set_rate = clk_stm32_composite_set_rate,
|
||||
.recalc_rate = clk_stm32_composite_recalc_rate,
|
||||
.round_rate = clk_stm32_composite_round_rate,
|
||||
.get_parent = clk_stm32_composite_get_parent,
|
||||
.set_parent = clk_stm32_composite_set_parent,
|
||||
.enable = clk_stm32_composite_gate_enable,
|
||||
.disable = clk_stm32_composite_gate_disable,
|
||||
.is_enabled = clk_stm32_composite_is_enabled,
|
||||
.disable_unused = clk_stm32_composite_disable_unused,
|
||||
};
|
||||
|
||||
struct clk_hw *clk_stm32_mux_register(struct device *dev,
|
||||
const struct stm32_rcc_match_data *data,
|
||||
void __iomem *base,
|
||||
spinlock_t *lock,
|
||||
const struct clock_config *cfg)
|
||||
{
|
||||
struct clk_stm32_mux *mux = cfg->clock_cfg;
|
||||
struct clk_hw *hw = &mux->hw;
|
||||
int err;
|
||||
|
||||
mux->base = base;
|
||||
mux->lock = lock;
|
||||
mux->clock_data = data->clock_data;
|
||||
|
||||
err = clk_hw_register(dev, hw);
|
||||
if (err)
|
||||
return ERR_PTR(err);
|
||||
|
||||
return hw;
|
||||
}
|
||||
|
||||
struct clk_hw *clk_stm32_gate_register(struct device *dev,
|
||||
const struct stm32_rcc_match_data *data,
|
||||
void __iomem *base,
|
||||
spinlock_t *lock,
|
||||
const struct clock_config *cfg)
|
||||
{
|
||||
struct clk_stm32_gate *gate = cfg->clock_cfg;
|
||||
struct clk_hw *hw = &gate->hw;
|
||||
int err;
|
||||
|
||||
gate->base = base;
|
||||
gate->lock = lock;
|
||||
gate->clock_data = data->clock_data;
|
||||
|
||||
err = clk_hw_register(dev, hw);
|
||||
if (err)
|
||||
return ERR_PTR(err);
|
||||
|
||||
return hw;
|
||||
}
|
||||
|
||||
struct clk_hw *clk_stm32_div_register(struct device *dev,
|
||||
const struct stm32_rcc_match_data *data,
|
||||
void __iomem *base,
|
||||
spinlock_t *lock,
|
||||
const struct clock_config *cfg)
|
||||
{
|
||||
struct clk_stm32_div *div = cfg->clock_cfg;
|
||||
struct clk_hw *hw = &div->hw;
|
||||
int err;
|
||||
|
||||
div->base = base;
|
||||
div->lock = lock;
|
||||
div->clock_data = data->clock_data;
|
||||
|
||||
err = clk_hw_register(dev, hw);
|
||||
if (err)
|
||||
return ERR_PTR(err);
|
||||
|
||||
return hw;
|
||||
}
|
||||
|
||||
struct clk_hw *clk_stm32_composite_register(struct device *dev,
|
||||
const struct stm32_rcc_match_data *data,
|
||||
void __iomem *base,
|
||||
spinlock_t *lock,
|
||||
const struct clock_config *cfg)
|
||||
{
|
||||
struct clk_stm32_composite *composite = cfg->clock_cfg;
|
||||
struct clk_hw *hw = &composite->hw;
|
||||
int err;
|
||||
|
||||
composite->base = base;
|
||||
composite->lock = lock;
|
||||
composite->clock_data = data->clock_data;
|
||||
|
||||
err = clk_hw_register(dev, hw);
|
||||
if (err)
|
||||
return ERR_PTR(err);
|
||||
|
||||
return hw;
|
||||
}
|
||||
|
|
@ -0,0 +1,188 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
|
||||
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
|
||||
struct stm32_rcc_match_data;
|
||||
|
||||
struct stm32_mux_cfg {
|
||||
u16 offset;
|
||||
u8 shift;
|
||||
u8 width;
|
||||
u8 flags;
|
||||
u32 *table;
|
||||
u8 ready;
|
||||
};
|
||||
|
||||
struct stm32_gate_cfg {
|
||||
u16 offset;
|
||||
u8 bit_idx;
|
||||
u8 set_clr;
|
||||
};
|
||||
|
||||
struct stm32_div_cfg {
|
||||
u16 offset;
|
||||
u8 shift;
|
||||
u8 width;
|
||||
u8 flags;
|
||||
u8 ready;
|
||||
const struct clk_div_table *table;
|
||||
};
|
||||
|
||||
struct stm32_composite_cfg {
|
||||
int mux;
|
||||
int gate;
|
||||
int div;
|
||||
};
|
||||
|
||||
#define NO_ID 0xFFFFFFFF
|
||||
|
||||
#define NO_STM32_MUX 0xFFFF
|
||||
#define NO_STM32_DIV 0xFFFF
|
||||
#define NO_STM32_GATE 0xFFFF
|
||||
|
||||
struct clock_config {
|
||||
unsigned long id;
|
||||
int sec_id;
|
||||
void *clock_cfg;
|
||||
|
||||
struct clk_hw *(*func)(struct device *dev,
|
||||
const struct stm32_rcc_match_data *data,
|
||||
void __iomem *base,
|
||||
spinlock_t *lock,
|
||||
const struct clock_config *cfg);
|
||||
};
|
||||
|
||||
struct clk_stm32_clock_data {
|
||||
u16 *gate_cpt;
|
||||
const struct stm32_gate_cfg *gates;
|
||||
const struct stm32_mux_cfg *muxes;
|
||||
const struct stm32_div_cfg *dividers;
|
||||
struct clk_hw *(*is_multi_mux)(struct clk_hw *hw);
|
||||
};
|
||||
|
||||
struct stm32_rcc_match_data {
|
||||
struct clk_hw_onecell_data *hw_clks;
|
||||
unsigned int num_clocks;
|
||||
const struct clock_config *tab_clocks;
|
||||
unsigned int maxbinding;
|
||||
struct clk_stm32_clock_data *clock_data;
|
||||
u32 clear_offset;
|
||||
int (*check_security)(void __iomem *base,
|
||||
const struct clock_config *cfg);
|
||||
int (*multi_mux)(void __iomem *base, const struct clock_config *cfg);
|
||||
};
|
||||
|
||||
int stm32_rcc_reset_init(struct device *dev, const struct of_device_id *match,
|
||||
void __iomem *base);
|
||||
|
||||
int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data,
|
||||
void __iomem *base);
|
||||
|
||||
/* MUX define */
|
||||
#define MUX_NO_RDY 0xFF
|
||||
#define MUX_SAFE BIT(7)
|
||||
|
||||
/* DIV define */
|
||||
#define DIV_NO_RDY 0xFF
|
||||
|
||||
/* Definition of clock structure */
|
||||
struct clk_stm32_mux {
|
||||
u16 mux_id;
|
||||
struct clk_hw hw;
|
||||
void __iomem *base;
|
||||
struct clk_stm32_clock_data *clock_data;
|
||||
spinlock_t *lock; /* spin lock */
|
||||
};
|
||||
|
||||
#define to_clk_stm32_mux(_hw) container_of(_hw, struct clk_stm32_mux, hw)
|
||||
|
||||
struct clk_stm32_gate {
|
||||
u16 gate_id;
|
||||
struct clk_hw hw;
|
||||
void __iomem *base;
|
||||
struct clk_stm32_clock_data *clock_data;
|
||||
spinlock_t *lock; /* spin lock */
|
||||
};
|
||||
|
||||
#define to_clk_stm32_gate(_hw) container_of(_hw, struct clk_stm32_gate, hw)
|
||||
|
||||
struct clk_stm32_div {
|
||||
u16 div_id;
|
||||
struct clk_hw hw;
|
||||
void __iomem *base;
|
||||
struct clk_stm32_clock_data *clock_data;
|
||||
spinlock_t *lock; /* spin lock */
|
||||
};
|
||||
|
||||
#define to_clk_stm32_divider(_hw) container_of(_hw, struct clk_stm32_div, hw)
|
||||
|
||||
struct clk_stm32_composite {
|
||||
u16 gate_id;
|
||||
u16 mux_id;
|
||||
u16 div_id;
|
||||
struct clk_hw hw;
|
||||
void __iomem *base;
|
||||
struct clk_stm32_clock_data *clock_data;
|
||||
spinlock_t *lock; /* spin lock */
|
||||
};
|
||||
|
||||
#define to_clk_stm32_composite(_hw) container_of(_hw, struct clk_stm32_composite, hw)
|
||||
|
||||
/* Clock operators */
|
||||
extern const struct clk_ops clk_stm32_mux_ops;
|
||||
extern const struct clk_ops clk_stm32_gate_ops;
|
||||
extern const struct clk_ops clk_stm32_divider_ops;
|
||||
extern const struct clk_ops clk_stm32_composite_ops;
|
||||
|
||||
/* Clock registering */
|
||||
struct clk_hw *clk_stm32_mux_register(struct device *dev,
|
||||
const struct stm32_rcc_match_data *data,
|
||||
void __iomem *base,
|
||||
spinlock_t *lock,
|
||||
const struct clock_config *cfg);
|
||||
|
||||
struct clk_hw *clk_stm32_gate_register(struct device *dev,
|
||||
const struct stm32_rcc_match_data *data,
|
||||
void __iomem *base,
|
||||
spinlock_t *lock,
|
||||
const struct clock_config *cfg);
|
||||
|
||||
struct clk_hw *clk_stm32_div_register(struct device *dev,
|
||||
const struct stm32_rcc_match_data *data,
|
||||
void __iomem *base,
|
||||
spinlock_t *lock,
|
||||
const struct clock_config *cfg);
|
||||
|
||||
struct clk_hw *clk_stm32_composite_register(struct device *dev,
|
||||
const struct stm32_rcc_match_data *data,
|
||||
void __iomem *base,
|
||||
spinlock_t *lock,
|
||||
const struct clock_config *cfg);
|
||||
|
||||
#define STM32_CLOCK_CFG(_binding, _clk, _sec_id, _struct, _register)\
|
||||
{\
|
||||
.id = (_binding),\
|
||||
.sec_id = (_sec_id),\
|
||||
.clock_cfg = (_struct) {_clk},\
|
||||
.func = (_register),\
|
||||
}
|
||||
|
||||
#define STM32_MUX_CFG(_binding, _clk, _sec_id)\
|
||||
STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_mux *,\
|
||||
&clk_stm32_mux_register)
|
||||
|
||||
#define STM32_GATE_CFG(_binding, _clk, _sec_id)\
|
||||
STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_gate *,\
|
||||
&clk_stm32_gate_register)
|
||||
|
||||
#define STM32_DIV_CFG(_binding, _clk, _sec_id)\
|
||||
STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_div *,\
|
||||
&clk_stm32_div_register)
|
||||
|
||||
#define STM32_COMPOSITE_CFG(_binding, _clk, _sec_id)\
|
||||
STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_composite *,\
|
||||
&clk_stm32_composite_register)
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,122 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
|
||||
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include "clk-stm32-core.h"
|
||||
|
||||
#define STM32_RESET_ID_MASK GENMASK(15, 0)
|
||||
|
||||
struct stm32_reset_data {
|
||||
/* reset lock */
|
||||
spinlock_t lock;
|
||||
struct reset_controller_dev rcdev;
|
||||
void __iomem *membase;
|
||||
u32 clear_offset;
|
||||
};
|
||||
|
||||
static inline struct stm32_reset_data *
|
||||
to_stm32_reset_data(struct reset_controller_dev *rcdev)
|
||||
{
|
||||
return container_of(rcdev, struct stm32_reset_data, rcdev);
|
||||
}
|
||||
|
||||
static int stm32_reset_update(struct reset_controller_dev *rcdev,
|
||||
unsigned long id, bool assert)
|
||||
{
|
||||
struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
|
||||
int reg_width = sizeof(u32);
|
||||
int bank = id / (reg_width * BITS_PER_BYTE);
|
||||
int offset = id % (reg_width * BITS_PER_BYTE);
|
||||
|
||||
if (data->clear_offset) {
|
||||
void __iomem *addr;
|
||||
|
||||
addr = data->membase + (bank * reg_width);
|
||||
if (!assert)
|
||||
addr += data->clear_offset;
|
||||
|
||||
writel(BIT(offset), addr);
|
||||
|
||||
} else {
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
|
||||
spin_lock_irqsave(&data->lock, flags);
|
||||
|
||||
reg = readl(data->membase + (bank * reg_width));
|
||||
|
||||
if (assert)
|
||||
reg |= BIT(offset);
|
||||
else
|
||||
reg &= ~BIT(offset);
|
||||
|
||||
writel(reg, data->membase + (bank * reg_width));
|
||||
|
||||
spin_unlock_irqrestore(&data->lock, flags);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_reset_assert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
return stm32_reset_update(rcdev, id, true);
|
||||
}
|
||||
|
||||
static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
return stm32_reset_update(rcdev, id, false);
|
||||
}
|
||||
|
||||
static int stm32_reset_status(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
|
||||
int reg_width = sizeof(u32);
|
||||
int bank = id / (reg_width * BITS_PER_BYTE);
|
||||
int offset = id % (reg_width * BITS_PER_BYTE);
|
||||
u32 reg;
|
||||
|
||||
reg = readl(data->membase + (bank * reg_width));
|
||||
|
||||
return !!(reg & BIT(offset));
|
||||
}
|
||||
|
||||
static const struct reset_control_ops stm32_reset_ops = {
|
||||
.assert = stm32_reset_assert,
|
||||
.deassert = stm32_reset_deassert,
|
||||
.status = stm32_reset_status,
|
||||
};
|
||||
|
||||
int stm32_rcc_reset_init(struct device *dev, const struct of_device_id *match,
|
||||
void __iomem *base)
|
||||
{
|
||||
const struct stm32_rcc_match_data *data = match->data;
|
||||
struct stm32_reset_data *reset_data = NULL;
|
||||
|
||||
data = match->data;
|
||||
|
||||
reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
|
||||
if (!reset_data)
|
||||
return -ENOMEM;
|
||||
|
||||
reset_data->membase = base;
|
||||
reset_data->rcdev.owner = THIS_MODULE;
|
||||
reset_data->rcdev.ops = &stm32_reset_ops;
|
||||
reset_data->rcdev.of_node = dev_of_node(dev);
|
||||
reset_data->rcdev.nr_resets = STM32_RESET_ID_MASK;
|
||||
reset_data->clear_offset = data->clear_offset;
|
||||
|
||||
return reset_controller_register(&reset_data->rcdev);
|
||||
}
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
|
||||
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
int stm32_rcc_reset_init(struct device *dev, const struct of_device_id *match,
|
||||
void __iomem *base);
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,299 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2022 Samsung Electronics Co., Ltd.
|
||||
* Author: Chanho Park <chanho61.park@samsung.com>
|
||||
*
|
||||
* Device Tree binding constants for Exynos Auto V9 clock controller.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H
|
||||
#define _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H
|
||||
|
||||
/* CMU_TOP */
|
||||
#define FOUT_SHARED0_PLL 1
|
||||
#define FOUT_SHARED1_PLL 2
|
||||
#define FOUT_SHARED2_PLL 3
|
||||
#define FOUT_SHARED3_PLL 4
|
||||
#define FOUT_SHARED4_PLL 5
|
||||
|
||||
/* MUX in CMU_TOP */
|
||||
#define MOUT_SHARED0_PLL 6
|
||||
#define MOUT_SHARED1_PLL 7
|
||||
#define MOUT_SHARED2_PLL 8
|
||||
#define MOUT_SHARED3_PLL 9
|
||||
#define MOUT_SHARED4_PLL 10
|
||||
#define MOUT_CLKCMU_CMU_BOOST 11
|
||||
#define MOUT_CLKCMU_CMU_CMUREF 12
|
||||
#define MOUT_CLKCMU_ACC_BUS 13
|
||||
#define MOUT_CLKCMU_APM_BUS 14
|
||||
#define MOUT_CLKCMU_AUD_CPU 15
|
||||
#define MOUT_CLKCMU_AUD_BUS 16
|
||||
#define MOUT_CLKCMU_BUSC_BUS 17
|
||||
#define MOUT_CLKCMU_BUSMC_BUS 19
|
||||
#define MOUT_CLKCMU_CORE_BUS 20
|
||||
#define MOUT_CLKCMU_CPUCL0_SWITCH 21
|
||||
#define MOUT_CLKCMU_CPUCL0_CLUSTER 22
|
||||
#define MOUT_CLKCMU_CPUCL1_SWITCH 24
|
||||
#define MOUT_CLKCMU_CPUCL1_CLUSTER 25
|
||||
#define MOUT_CLKCMU_DPTX_BUS 26
|
||||
#define MOUT_CLKCMU_DPTX_DPGTC 27
|
||||
#define MOUT_CLKCMU_DPUM_BUS 28
|
||||
#define MOUT_CLKCMU_DPUS0_BUS 29
|
||||
#define MOUT_CLKCMU_DPUS1_BUS 30
|
||||
#define MOUT_CLKCMU_FSYS0_BUS 31
|
||||
#define MOUT_CLKCMU_FSYS0_PCIE 32
|
||||
#define MOUT_CLKCMU_FSYS1_BUS 33
|
||||
#define MOUT_CLKCMU_FSYS1_USBDRD 34
|
||||
#define MOUT_CLKCMU_FSYS1_MMC_CARD 35
|
||||
#define MOUT_CLKCMU_FSYS2_BUS 36
|
||||
#define MOUT_CLKCMU_FSYS2_UFS_EMBD 37
|
||||
#define MOUT_CLKCMU_FSYS2_ETHERNET 38
|
||||
#define MOUT_CLKCMU_G2D_G2D 39
|
||||
#define MOUT_CLKCMU_G2D_MSCL 40
|
||||
#define MOUT_CLKCMU_G3D00_SWITCH 41
|
||||
#define MOUT_CLKCMU_G3D01_SWITCH 42
|
||||
#define MOUT_CLKCMU_G3D1_SWITCH 43
|
||||
#define MOUT_CLKCMU_ISPB_BUS 44
|
||||
#define MOUT_CLKCMU_MFC_MFC 45
|
||||
#define MOUT_CLKCMU_MFC_WFD 46
|
||||
#define MOUT_CLKCMU_MIF_SWITCH 47
|
||||
#define MOUT_CLKCMU_MIF_BUSP 48
|
||||
#define MOUT_CLKCMU_NPU_BUS 49
|
||||
#define MOUT_CLKCMU_PERIC0_BUS 50
|
||||
#define MOUT_CLKCMU_PERIC0_IP 51
|
||||
#define MOUT_CLKCMU_PERIC1_BUS 52
|
||||
#define MOUT_CLKCMU_PERIC1_IP 53
|
||||
#define MOUT_CLKCMU_PERIS_BUS 54
|
||||
|
||||
/* DIV in CMU_TOP */
|
||||
#define DOUT_SHARED0_DIV3 101
|
||||
#define DOUT_SHARED0_DIV2 102
|
||||
#define DOUT_SHARED1_DIV3 103
|
||||
#define DOUT_SHARED1_DIV2 104
|
||||
#define DOUT_SHARED1_DIV4 105
|
||||
#define DOUT_SHARED2_DIV3 106
|
||||
#define DOUT_SHARED2_DIV2 107
|
||||
#define DOUT_SHARED2_DIV4 108
|
||||
#define DOUT_SHARED4_DIV2 109
|
||||
#define DOUT_SHARED4_DIV4 110
|
||||
#define DOUT_CLKCMU_CMU_BOOST 111
|
||||
#define DOUT_CLKCMU_ACC_BUS 112
|
||||
#define DOUT_CLKCMU_APM_BUS 113
|
||||
#define DOUT_CLKCMU_AUD_CPU 114
|
||||
#define DOUT_CLKCMU_AUD_BUS 115
|
||||
#define DOUT_CLKCMU_BUSC_BUS 116
|
||||
#define DOUT_CLKCMU_BUSMC_BUS 118
|
||||
#define DOUT_CLKCMU_CORE_BUS 119
|
||||
#define DOUT_CLKCMU_CPUCL0_SWITCH 120
|
||||
#define DOUT_CLKCMU_CPUCL0_CLUSTER 121
|
||||
#define DOUT_CLKCMU_CPUCL1_SWITCH 123
|
||||
#define DOUT_CLKCMU_CPUCL1_CLUSTER 124
|
||||
#define DOUT_CLKCMU_DPTX_BUS 125
|
||||
#define DOUT_CLKCMU_DPTX_DPGTC 126
|
||||
#define DOUT_CLKCMU_DPUM_BUS 127
|
||||
#define DOUT_CLKCMU_DPUS0_BUS 128
|
||||
#define DOUT_CLKCMU_DPUS1_BUS 129
|
||||
#define DOUT_CLKCMU_FSYS0_BUS 130
|
||||
#define DOUT_CLKCMU_FSYS0_PCIE 131
|
||||
#define DOUT_CLKCMU_FSYS1_BUS 132
|
||||
#define DOUT_CLKCMU_FSYS1_USBDRD 133
|
||||
#define DOUT_CLKCMU_FSYS2_BUS 134
|
||||
#define DOUT_CLKCMU_FSYS2_UFS_EMBD 135
|
||||
#define DOUT_CLKCMU_FSYS2_ETHERNET 136
|
||||
#define DOUT_CLKCMU_G2D_G2D 137
|
||||
#define DOUT_CLKCMU_G2D_MSCL 138
|
||||
#define DOUT_CLKCMU_G3D00_SWITCH 139
|
||||
#define DOUT_CLKCMU_G3D01_SWITCH 140
|
||||
#define DOUT_CLKCMU_G3D1_SWITCH 141
|
||||
#define DOUT_CLKCMU_ISPB_BUS 142
|
||||
#define DOUT_CLKCMU_MFC_MFC 143
|
||||
#define DOUT_CLKCMU_MFC_WFD 144
|
||||
#define DOUT_CLKCMU_MIF_SWITCH 145
|
||||
#define DOUT_CLKCMU_MIF_BUSP 146
|
||||
#define DOUT_CLKCMU_NPU_BUS 147
|
||||
#define DOUT_CLKCMU_PERIC0_BUS 148
|
||||
#define DOUT_CLKCMU_PERIC0_IP 149
|
||||
#define DOUT_CLKCMU_PERIC1_BUS 150
|
||||
#define DOUT_CLKCMU_PERIC1_IP 151
|
||||
#define DOUT_CLKCMU_PERIS_BUS 152
|
||||
|
||||
/* GAT in CMU_TOP */
|
||||
#define GOUT_CLKCMU_CMU_BOOST 201
|
||||
#define GOUT_CLKCMU_CPUCL0_BOOST 202
|
||||
#define GOUT_CLKCMU_CPUCL1_BOOST 203
|
||||
#define GOUT_CLKCMU_CORE_BOOST 204
|
||||
#define GOUT_CLKCMU_BUSC_BOOST 205
|
||||
#define GOUT_CLKCMU_BUSMC_BOOST 206
|
||||
#define GOUT_CLKCMU_MIF_BOOST 207
|
||||
#define GOUT_CLKCMU_ACC_BUS 208
|
||||
#define GOUT_CLKCMU_APM_BUS 209
|
||||
#define GOUT_CLKCMU_AUD_CPU 210
|
||||
#define GOUT_CLKCMU_AUD_BUS 211
|
||||
#define GOUT_CLKCMU_BUSC_BUS 212
|
||||
#define GOUT_CLKCMU_BUSMC_BUS 214
|
||||
#define GOUT_CLKCMU_CORE_BUS 215
|
||||
#define GOUT_CLKCMU_CPUCL0_SWITCH 216
|
||||
#define GOUT_CLKCMU_CPUCL0_CLUSTER 217
|
||||
#define GOUT_CLKCMU_CPUCL1_SWITCH 219
|
||||
#define GOUT_CLKCMU_CPUCL1_CLUSTER 220
|
||||
#define GOUT_CLKCMU_DPTX_BUS 221
|
||||
#define GOUT_CLKCMU_DPTX_DPGTC 222
|
||||
#define GOUT_CLKCMU_DPUM_BUS 223
|
||||
#define GOUT_CLKCMU_DPUS0_BUS 224
|
||||
#define GOUT_CLKCMU_DPUS1_BUS 225
|
||||
#define GOUT_CLKCMU_FSYS0_BUS 226
|
||||
#define GOUT_CLKCMU_FSYS0_PCIE 227
|
||||
#define GOUT_CLKCMU_FSYS1_BUS 228
|
||||
#define GOUT_CLKCMU_FSYS1_USBDRD 229
|
||||
#define GOUT_CLKCMU_FSYS1_MMC_CARD 230
|
||||
#define GOUT_CLKCMU_FSYS2_BUS 231
|
||||
#define GOUT_CLKCMU_FSYS2_UFS_EMBD 232
|
||||
#define GOUT_CLKCMU_FSYS2_ETHERNET 233
|
||||
#define GOUT_CLKCMU_G2D_G2D 234
|
||||
#define GOUT_CLKCMU_G2D_MSCL 235
|
||||
#define GOUT_CLKCMU_G3D00_SWITCH 236
|
||||
#define GOUT_CLKCMU_G3D01_SWITCH 237
|
||||
#define GOUT_CLKCMU_G3D1_SWITCH 238
|
||||
#define GOUT_CLKCMU_ISPB_BUS 239
|
||||
#define GOUT_CLKCMU_MFC_MFC 240
|
||||
#define GOUT_CLKCMU_MFC_WFD 241
|
||||
#define GOUT_CLKCMU_MIF_SWITCH 242
|
||||
#define GOUT_CLKCMU_MIF_BUSP 243
|
||||
#define GOUT_CLKCMU_NPU_BUS 244
|
||||
#define GOUT_CLKCMU_PERIC0_BUS 245
|
||||
#define GOUT_CLKCMU_PERIC0_IP 246
|
||||
#define GOUT_CLKCMU_PERIC1_BUS 247
|
||||
#define GOUT_CLKCMU_PERIC1_IP 248
|
||||
#define GOUT_CLKCMU_PERIS_BUS 249
|
||||
|
||||
#define TOP_NR_CLK 250
|
||||
|
||||
/* CMU_BUSMC */
|
||||
#define CLK_MOUT_BUSMC_BUS_USER 1
|
||||
#define CLK_DOUT_BUSMC_BUSP 2
|
||||
#define CLK_GOUT_BUSMC_PDMA0_PCLK 3
|
||||
#define CLK_GOUT_BUSMC_SPDMA_PCLK 4
|
||||
|
||||
#define BUSMC_NR_CLK 5
|
||||
|
||||
/* CMU_CORE */
|
||||
#define CLK_MOUT_CORE_BUS_USER 1
|
||||
#define CLK_DOUT_CORE_BUSP 2
|
||||
#define CLK_GOUT_CORE_CCI_CLK 3
|
||||
#define CLK_GOUT_CORE_CCI_PCLK 4
|
||||
#define CLK_GOUT_CORE_CMU_CORE_PCLK 5
|
||||
|
||||
#define CORE_NR_CLK 6
|
||||
|
||||
/* CMU_FSYS2 */
|
||||
#define CLK_MOUT_FSYS2_BUS_USER 1
|
||||
#define CLK_MOUT_FSYS2_UFS_EMBD_USER 2
|
||||
#define CLK_MOUT_FSYS2_ETHERNET_USER 3
|
||||
#define CLK_GOUT_FSYS2_UFS_EMBD0_ACLK 4
|
||||
#define CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO 5
|
||||
#define CLK_GOUT_FSYS2_UFS_EMBD1_ACLK 6
|
||||
#define CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO 7
|
||||
|
||||
#define FSYS2_NR_CLK 8
|
||||
|
||||
/* CMU_PERIC0 */
|
||||
#define CLK_MOUT_PERIC0_BUS_USER 1
|
||||
#define CLK_MOUT_PERIC0_IP_USER 2
|
||||
#define CLK_MOUT_PERIC0_USI00_USI 3
|
||||
#define CLK_MOUT_PERIC0_USI01_USI 4
|
||||
#define CLK_MOUT_PERIC0_USI02_USI 5
|
||||
#define CLK_MOUT_PERIC0_USI03_USI 6
|
||||
#define CLK_MOUT_PERIC0_USI04_USI 7
|
||||
#define CLK_MOUT_PERIC0_USI05_USI 8
|
||||
#define CLK_MOUT_PERIC0_USI_I2C 9
|
||||
|
||||
#define CLK_DOUT_PERIC0_USI00_USI 10
|
||||
#define CLK_DOUT_PERIC0_USI01_USI 11
|
||||
#define CLK_DOUT_PERIC0_USI02_USI 12
|
||||
#define CLK_DOUT_PERIC0_USI03_USI 13
|
||||
#define CLK_DOUT_PERIC0_USI04_USI 14
|
||||
#define CLK_DOUT_PERIC0_USI05_USI 15
|
||||
#define CLK_DOUT_PERIC0_USI_I2C 16
|
||||
|
||||
#define CLK_GOUT_PERIC0_IPCLK_0 20
|
||||
#define CLK_GOUT_PERIC0_IPCLK_1 21
|
||||
#define CLK_GOUT_PERIC0_IPCLK_2 22
|
||||
#define CLK_GOUT_PERIC0_IPCLK_3 23
|
||||
#define CLK_GOUT_PERIC0_IPCLK_4 24
|
||||
#define CLK_GOUT_PERIC0_IPCLK_5 25
|
||||
#define CLK_GOUT_PERIC0_IPCLK_6 26
|
||||
#define CLK_GOUT_PERIC0_IPCLK_7 27
|
||||
#define CLK_GOUT_PERIC0_IPCLK_8 28
|
||||
#define CLK_GOUT_PERIC0_IPCLK_9 29
|
||||
#define CLK_GOUT_PERIC0_IPCLK_10 30
|
||||
#define CLK_GOUT_PERIC0_IPCLK_11 30
|
||||
#define CLK_GOUT_PERIC0_PCLK_0 31
|
||||
#define CLK_GOUT_PERIC0_PCLK_1 32
|
||||
#define CLK_GOUT_PERIC0_PCLK_2 33
|
||||
#define CLK_GOUT_PERIC0_PCLK_3 34
|
||||
#define CLK_GOUT_PERIC0_PCLK_4 35
|
||||
#define CLK_GOUT_PERIC0_PCLK_5 36
|
||||
#define CLK_GOUT_PERIC0_PCLK_6 37
|
||||
#define CLK_GOUT_PERIC0_PCLK_7 38
|
||||
#define CLK_GOUT_PERIC0_PCLK_8 39
|
||||
#define CLK_GOUT_PERIC0_PCLK_9 40
|
||||
#define CLK_GOUT_PERIC0_PCLK_10 41
|
||||
#define CLK_GOUT_PERIC0_PCLK_11 42
|
||||
|
||||
#define PERIC0_NR_CLK 43
|
||||
|
||||
/* CMU_PERIC1 */
|
||||
#define CLK_MOUT_PERIC1_BUS_USER 1
|
||||
#define CLK_MOUT_PERIC1_IP_USER 2
|
||||
#define CLK_MOUT_PERIC1_USI06_USI 3
|
||||
#define CLK_MOUT_PERIC1_USI07_USI 4
|
||||
#define CLK_MOUT_PERIC1_USI08_USI 5
|
||||
#define CLK_MOUT_PERIC1_USI09_USI 6
|
||||
#define CLK_MOUT_PERIC1_USI10_USI 7
|
||||
#define CLK_MOUT_PERIC1_USI11_USI 8
|
||||
#define CLK_MOUT_PERIC1_USI_I2C 9
|
||||
|
||||
#define CLK_DOUT_PERIC1_USI06_USI 10
|
||||
#define CLK_DOUT_PERIC1_USI07_USI 11
|
||||
#define CLK_DOUT_PERIC1_USI08_USI 12
|
||||
#define CLK_DOUT_PERIC1_USI09_USI 13
|
||||
#define CLK_DOUT_PERIC1_USI10_USI 14
|
||||
#define CLK_DOUT_PERIC1_USI11_USI 15
|
||||
#define CLK_DOUT_PERIC1_USI_I2C 16
|
||||
|
||||
#define CLK_GOUT_PERIC1_IPCLK_0 20
|
||||
#define CLK_GOUT_PERIC1_IPCLK_1 21
|
||||
#define CLK_GOUT_PERIC1_IPCLK_2 22
|
||||
#define CLK_GOUT_PERIC1_IPCLK_3 23
|
||||
#define CLK_GOUT_PERIC1_IPCLK_4 24
|
||||
#define CLK_GOUT_PERIC1_IPCLK_5 25
|
||||
#define CLK_GOUT_PERIC1_IPCLK_6 26
|
||||
#define CLK_GOUT_PERIC1_IPCLK_7 27
|
||||
#define CLK_GOUT_PERIC1_IPCLK_8 28
|
||||
#define CLK_GOUT_PERIC1_IPCLK_9 29
|
||||
#define CLK_GOUT_PERIC1_IPCLK_10 30
|
||||
#define CLK_GOUT_PERIC1_IPCLK_11 30
|
||||
#define CLK_GOUT_PERIC1_PCLK_0 31
|
||||
#define CLK_GOUT_PERIC1_PCLK_1 32
|
||||
#define CLK_GOUT_PERIC1_PCLK_2 33
|
||||
#define CLK_GOUT_PERIC1_PCLK_3 34
|
||||
#define CLK_GOUT_PERIC1_PCLK_4 35
|
||||
#define CLK_GOUT_PERIC1_PCLK_5 36
|
||||
#define CLK_GOUT_PERIC1_PCLK_6 37
|
||||
#define CLK_GOUT_PERIC1_PCLK_7 38
|
||||
#define CLK_GOUT_PERIC1_PCLK_8 39
|
||||
#define CLK_GOUT_PERIC1_PCLK_9 40
|
||||
#define CLK_GOUT_PERIC1_PCLK_10 41
|
||||
#define CLK_GOUT_PERIC1_PCLK_11 42
|
||||
|
||||
#define PERIC1_NR_CLK 43
|
||||
|
||||
/* CMU_PERIS */
|
||||
#define CLK_MOUT_PERIS_BUS_USER 1
|
||||
#define CLK_GOUT_SYSREG_PERIS_PCLK 2
|
||||
#define CLK_GOUT_WDT_CLUSTER0 3
|
||||
#define CLK_GOUT_WDT_CLUSTER1 4
|
||||
|
||||
#define PERIS_NR_CLK 5
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H */
|
||||
|
|
@ -0,0 +1,229 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ or BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2020 - All Rights Reserved
|
||||
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_STM32MP13_CLKS_H_
|
||||
#define _DT_BINDINGS_STM32MP13_CLKS_H_
|
||||
|
||||
/* OSCILLATOR clocks */
|
||||
#define CK_HSE 0
|
||||
#define CK_CSI 1
|
||||
#define CK_LSI 2
|
||||
#define CK_LSE 3
|
||||
#define CK_HSI 4
|
||||
#define CK_HSE_DIV2 5
|
||||
|
||||
/* PLL */
|
||||
#define PLL1 6
|
||||
#define PLL2 7
|
||||
#define PLL3 8
|
||||
#define PLL4 9
|
||||
|
||||
/* ODF */
|
||||
#define PLL1_P 10
|
||||
#define PLL1_Q 11
|
||||
#define PLL1_R 12
|
||||
#define PLL2_P 13
|
||||
#define PLL2_Q 14
|
||||
#define PLL2_R 15
|
||||
#define PLL3_P 16
|
||||
#define PLL3_Q 17
|
||||
#define PLL3_R 18
|
||||
#define PLL4_P 19
|
||||
#define PLL4_Q 20
|
||||
#define PLL4_R 21
|
||||
|
||||
#define PCLK1 22
|
||||
#define PCLK2 23
|
||||
#define PCLK3 24
|
||||
#define PCLK4 25
|
||||
#define PCLK5 26
|
||||
#define PCLK6 27
|
||||
|
||||
/* SYSTEM CLOCK */
|
||||
#define CK_PER 28
|
||||
#define CK_MPU 29
|
||||
#define CK_AXI 30
|
||||
#define CK_MLAHB 31
|
||||
|
||||
/* BASE TIMER */
|
||||
#define CK_TIMG1 32
|
||||
#define CK_TIMG2 33
|
||||
#define CK_TIMG3 34
|
||||
|
||||
/* AUX */
|
||||
#define RTC 35
|
||||
|
||||
/* TRACE & DEBUG clocks */
|
||||
#define CK_DBG 36
|
||||
#define CK_TRACE 37
|
||||
|
||||
/* MCO clocks */
|
||||
#define CK_MCO1 38
|
||||
#define CK_MCO2 39
|
||||
|
||||
/* IP clocks */
|
||||
#define SYSCFG 40
|
||||
#define VREF 41
|
||||
#define DTS 42
|
||||
#define PMBCTRL 43
|
||||
#define HDP 44
|
||||
#define IWDG2 45
|
||||
#define STGENRO 46
|
||||
#define USART1 47
|
||||
#define RTCAPB 48
|
||||
#define TZC 49
|
||||
#define TZPC 50
|
||||
#define IWDG1 51
|
||||
#define BSEC 52
|
||||
#define DMA1 53
|
||||
#define DMA2 54
|
||||
#define DMAMUX1 55
|
||||
#define DMAMUX2 56
|
||||
#define GPIOA 57
|
||||
#define GPIOB 58
|
||||
#define GPIOC 59
|
||||
#define GPIOD 60
|
||||
#define GPIOE 61
|
||||
#define GPIOF 62
|
||||
#define GPIOG 63
|
||||
#define GPIOH 64
|
||||
#define GPIOI 65
|
||||
#define CRYP1 66
|
||||
#define HASH1 67
|
||||
#define BKPSRAM 68
|
||||
#define MDMA 69
|
||||
#define CRC1 70
|
||||
#define USBH 71
|
||||
#define DMA3 72
|
||||
#define TSC 73
|
||||
#define PKA 74
|
||||
#define AXIMC 75
|
||||
#define MCE 76
|
||||
#define ETH1TX 77
|
||||
#define ETH2TX 78
|
||||
#define ETH1RX 79
|
||||
#define ETH2RX 80
|
||||
#define ETH1MAC 81
|
||||
#define ETH2MAC 82
|
||||
#define ETH1STP 83
|
||||
#define ETH2STP 84
|
||||
|
||||
/* IP clocks with parents */
|
||||
#define SDMMC1_K 85
|
||||
#define SDMMC2_K 86
|
||||
#define ADC1_K 87
|
||||
#define ADC2_K 88
|
||||
#define FMC_K 89
|
||||
#define QSPI_K 90
|
||||
#define RNG1_K 91
|
||||
#define USBPHY_K 92
|
||||
#define STGEN_K 93
|
||||
#define SPDIF_K 94
|
||||
#define SPI1_K 95
|
||||
#define SPI2_K 96
|
||||
#define SPI3_K 97
|
||||
#define SPI4_K 98
|
||||
#define SPI5_K 99
|
||||
#define I2C1_K 100
|
||||
#define I2C2_K 101
|
||||
#define I2C3_K 102
|
||||
#define I2C4_K 103
|
||||
#define I2C5_K 104
|
||||
#define TIM2_K 105
|
||||
#define TIM3_K 106
|
||||
#define TIM4_K 107
|
||||
#define TIM5_K 108
|
||||
#define TIM6_K 109
|
||||
#define TIM7_K 110
|
||||
#define TIM12_K 111
|
||||
#define TIM13_K 112
|
||||
#define TIM14_K 113
|
||||
#define TIM1_K 114
|
||||
#define TIM8_K 115
|
||||
#define TIM15_K 116
|
||||
#define TIM16_K 117
|
||||
#define TIM17_K 118
|
||||
#define LPTIM1_K 119
|
||||
#define LPTIM2_K 120
|
||||
#define LPTIM3_K 121
|
||||
#define LPTIM4_K 122
|
||||
#define LPTIM5_K 123
|
||||
#define USART1_K 124
|
||||
#define USART2_K 125
|
||||
#define USART3_K 126
|
||||
#define UART4_K 127
|
||||
#define UART5_K 128
|
||||
#define USART6_K 129
|
||||
#define UART7_K 130
|
||||
#define UART8_K 131
|
||||
#define DFSDM_K 132
|
||||
#define FDCAN_K 133
|
||||
#define SAI1_K 134
|
||||
#define SAI2_K 135
|
||||
#define ADFSDM_K 136
|
||||
#define USBO_K 137
|
||||
#define LTDC_PX 138
|
||||
#define ETH1CK_K 139
|
||||
#define ETH1PTP_K 140
|
||||
#define ETH2CK_K 141
|
||||
#define ETH2PTP_K 142
|
||||
#define DCMIPP_K 143
|
||||
#define SAES_K 144
|
||||
#define DTS_K 145
|
||||
|
||||
/* DDR */
|
||||
#define DDRC1 146
|
||||
#define DDRC1LP 147
|
||||
#define DDRC2 148
|
||||
#define DDRC2LP 149
|
||||
#define DDRPHYC 150
|
||||
#define DDRPHYCLP 151
|
||||
#define DDRCAPB 152
|
||||
#define DDRCAPBLP 153
|
||||
#define AXIDCG 154
|
||||
#define DDRPHYCAPB 155
|
||||
#define DDRPHYCAPBLP 156
|
||||
#define DDRPERFM 157
|
||||
|
||||
#define ADC1 158
|
||||
#define ADC2 159
|
||||
#define SAI1 160
|
||||
#define SAI2 161
|
||||
|
||||
#define STM32MP1_LAST_CLK 162
|
||||
|
||||
/* SCMI clock identifiers */
|
||||
#define CK_SCMI_HSE 0
|
||||
#define CK_SCMI_HSI 1
|
||||
#define CK_SCMI_CSI 2
|
||||
#define CK_SCMI_LSE 3
|
||||
#define CK_SCMI_LSI 4
|
||||
#define CK_SCMI_HSE_DIV2 5
|
||||
#define CK_SCMI_PLL2_Q 6
|
||||
#define CK_SCMI_PLL2_R 7
|
||||
#define CK_SCMI_PLL3_P 8
|
||||
#define CK_SCMI_PLL3_Q 9
|
||||
#define CK_SCMI_PLL3_R 10
|
||||
#define CK_SCMI_PLL4_P 11
|
||||
#define CK_SCMI_PLL4_Q 12
|
||||
#define CK_SCMI_PLL4_R 13
|
||||
#define CK_SCMI_MPU 14
|
||||
#define CK_SCMI_AXI 15
|
||||
#define CK_SCMI_MLAHB 16
|
||||
#define CK_SCMI_CKPER 17
|
||||
#define CK_SCMI_PCLK1 18
|
||||
#define CK_SCMI_PCLK2 19
|
||||
#define CK_SCMI_PCLK3 20
|
||||
#define CK_SCMI_PCLK4 21
|
||||
#define CK_SCMI_PCLK5 22
|
||||
#define CK_SCMI_PCLK6 23
|
||||
#define CK_SCMI_CKTIMG1 24
|
||||
#define CK_SCMI_CKTIMG2 25
|
||||
#define CK_SCMI_CKTIMG3 26
|
||||
#define CK_SCMI_RTC 27
|
||||
#define CK_SCMI_RTCAPB 28
|
||||
|
||||
#endif /* _DT_BINDINGS_STM32MP13_CLKS_H_ */
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
|
||||
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_STM32MP13_RESET_H_
|
||||
#define _DT_BINDINGS_STM32MP13_RESET_H_
|
||||
|
||||
#define TIM2_R 13568
|
||||
#define TIM3_R 13569
|
||||
#define TIM4_R 13570
|
||||
#define TIM5_R 13571
|
||||
#define TIM6_R 13572
|
||||
#define TIM7_R 13573
|
||||
#define LPTIM1_R 13577
|
||||
#define SPI2_R 13579
|
||||
#define SPI3_R 13580
|
||||
#define USART3_R 13583
|
||||
#define UART4_R 13584
|
||||
#define UART5_R 13585
|
||||
#define UART7_R 13586
|
||||
#define UART8_R 13587
|
||||
#define I2C1_R 13589
|
||||
#define I2C2_R 13590
|
||||
#define SPDIF_R 13594
|
||||
#define TIM1_R 13632
|
||||
#define TIM8_R 13633
|
||||
#define SPI1_R 13640
|
||||
#define USART6_R 13645
|
||||
#define SAI1_R 13648
|
||||
#define SAI2_R 13649
|
||||
#define DFSDM_R 13652
|
||||
#define FDCAN_R 13656
|
||||
#define LPTIM2_R 13696
|
||||
#define LPTIM3_R 13697
|
||||
#define LPTIM4_R 13698
|
||||
#define LPTIM5_R 13699
|
||||
#define SYSCFG_R 13707
|
||||
#define VREF_R 13709
|
||||
#define DTS_R 13712
|
||||
#define PMBCTRL_R 13713
|
||||
#define LTDC_R 13760
|
||||
#define DCMIPP_R 13761
|
||||
#define DDRPERFM_R 13768
|
||||
#define USBPHY_R 13776
|
||||
#define STGEN_R 13844
|
||||
#define USART1_R 13888
|
||||
#define USART2_R 13889
|
||||
#define SPI4_R 13890
|
||||
#define SPI5_R 13891
|
||||
#define I2C3_R 13892
|
||||
#define I2C4_R 13893
|
||||
#define I2C5_R 13894
|
||||
#define TIM12_R 13895
|
||||
#define TIM13_R 13896
|
||||
#define TIM14_R 13897
|
||||
#define TIM15_R 13898
|
||||
#define TIM16_R 13899
|
||||
#define TIM17_R 13900
|
||||
#define DMA1_R 13952
|
||||
#define DMA2_R 13953
|
||||
#define DMAMUX1_R 13954
|
||||
#define DMA3_R 13955
|
||||
#define DMAMUX2_R 13956
|
||||
#define ADC1_R 13957
|
||||
#define ADC2_R 13958
|
||||
#define USBO_R 13960
|
||||
#define GPIOA_R 14080
|
||||
#define GPIOB_R 14081
|
||||
#define GPIOC_R 14082
|
||||
#define GPIOD_R 14083
|
||||
#define GPIOE_R 14084
|
||||
#define GPIOF_R 14085
|
||||
#define GPIOG_R 14086
|
||||
#define GPIOH_R 14087
|
||||
#define GPIOI_R 14088
|
||||
#define TSC_R 14095
|
||||
#define PKA_R 14146
|
||||
#define SAES_R 14147
|
||||
#define CRYP1_R 14148
|
||||
#define HASH1_R 14149
|
||||
#define RNG1_R 14150
|
||||
#define AXIMC_R 14160
|
||||
#define MDMA_R 14208
|
||||
#define MCE_R 14209
|
||||
#define ETH1MAC_R 14218
|
||||
#define FMC_R 14220
|
||||
#define QSPI_R 14222
|
||||
#define SDMMC1_R 14224
|
||||
#define SDMMC2_R 14225
|
||||
#define CRC1_R 14228
|
||||
#define USBH_R 14232
|
||||
#define ETH2MAC_R 14238
|
||||
|
||||
/* SCMI reset domain identifiers */
|
||||
#define RST_SCMI_LTDC 0
|
||||
#define RST_SCMI_MDMA 1
|
||||
|
||||
#endif /* _DT_BINDINGS_STM32MP13_RESET_H_ */
|
||||
Loading…
Reference in New Issue