Documentation: dt: add omap mailbox bindings
Add the device tree bindings document for OMAP2+ mailbox. Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Suman Anna
Tony Lindgren
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OMAP2+ Mailbox Driver
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=====================
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The OMAP mailbox hardware facilitates communication between different processors
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using a queued mailbox interrupt mechanism. The IP block is external to the
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various processor subsystems and is connected on an interconnect bus. The
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communication is achieved through a set of registers for message storage and
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interrupt configuration registers.
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Each mailbox IP block has a certain number of h/w fifo queues and output
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interrupt lines. An output interrupt line is routed to an interrupt controller
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within a processor subsystem, and there can be more than one line going to a
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specific processor's interrupt controller. The interrupt line connections are
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fixed for an instance and are dictated by the IP integration into the SoC
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(excluding the SoCs that have a Interrupt Crossbar IP). Each interrupt line is
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programmable through a set of interrupt configuration registers, and have a rx
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and tx interrupt source per h/w fifo. Communication between different processors
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is achieved through the appropriate programming of the rx and tx interrupt
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sources on the appropriate interrupt lines.
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The number of h/w fifo queues and interrupt lines dictate the usable registers.
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All the current OMAP SoCs except for the newest DRA7xx SoC has a single IP
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instance. DRA7xx has multiple instances with different number of h/w fifo queues
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and interrupt lines between different instances. The interrupt lines can also be
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routed to different processor sub-systems on DRA7xx as they are routed through
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the Crossbar, a kind of interrupt router/multiplexer.
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Mailbox Device Node:
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====================
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A Mailbox device node is used to represent a Mailbox IP instance within a SoC.
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The sub-mailboxes are represented as child nodes of this parent node.
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Required properties:
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--------------------
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- compatible: Should be one of the following,
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"ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs
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"ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
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"ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
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AM43xx and DRA7xx SoCs
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- reg: Contains the mailbox register address range (base
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address and length)
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- interrupts: Contains the interrupt information for the mailbox
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device. The format is dependent on which interrupt
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controller the OMAP device uses
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- ti,hwmods: Name of the hwmod associated with the mailbox
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- ti,mbox-num-users: Number of targets (processor devices) that the mailbox
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device can interrupt
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- ti,mbox-num-fifos: Number of h/w fifo queues within the mailbox IP block
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Child Nodes:
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============
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A child node is used for representing the actual sub-mailbox device that is
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used for the communication between the host processor and a remote processor.
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Each child node should have a unique node name across all the different
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mailbox device nodes.
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Required properties:
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--------------------
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- ti,mbox-tx: sub-mailbox descriptor property defining a Tx fifo
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- ti,mbox-rx: sub-mailbox descriptor property defining a Rx fifo
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Sub-mailbox Descriptor Data
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---------------------------
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Each of the above ti,mbox-tx and ti,mbox-rx properties should have 3 cells of
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data that represent the following:
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Cell #1 (fifo_id) - mailbox fifo id used either for transmitting
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(ti,mbox-tx) or for receiving (ti,mbox-rx)
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Cell #2 (irq_id) - irq identifier index number to use from the parent's
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interrupts data. Should be 0 for most of the cases, a
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positive index value is seen only on mailboxes that have
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multiple interrupt lines connected to the MPU processor.
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Cell #3 (usr_id) - mailbox user id for identifying the interrupt line
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associated with generating a tx/rx fifo interrupt.
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Example:
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--------
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/* OMAP4 */
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mailbox: mailbox@4a0f4000 {
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compatible = "ti,omap4-mailbox";
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reg = <0x4a0f4000 0x200>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "mailbox";
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ti,mbox-num-users = <3>;
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ti,mbox-num-fifos = <8>;
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mbox_ipu: mbox_ipu {
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ti,mbox-tx = <0 0 0>;
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ti,mbox-rx = <1 0 0>;
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};
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mbox_dsp: mbox_dsp {
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ti,mbox-tx = <3 0 0>;
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ti,mbox-rx = <2 0 0>;
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};
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};
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/* AM33xx */
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mailbox: mailbox@480C8000 {
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compatible = "ti,omap4-mailbox";
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reg = <0x480C8000 0x200>;
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interrupts = <77>;
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ti,hwmods = "mailbox";
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <8>;
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mbox_wkupm3: wkup_m3 {
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ti,mbox-tx = <0 0 0>;
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ti,mbox-rx = <0 0 3>;
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};
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};
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