Merge branch 'm7530-sw-fallback'
DENG Qingfang says:
====================
mt7530 software fallback bridging fix
DSA core has gained software fallback support since commit 2f5dc00f7a,
but it does not work properly on mt7530. This patch series fixes the
issues.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
d851798584
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@ -366,8 +366,8 @@ mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
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int i;
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reg[1] |= vid & CVID_MASK;
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if (vid > 1)
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reg[1] |= ATA2_IVL;
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reg[1] |= ATA2_IVL;
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reg[1] |= ATA2_FID(FID_BRIDGED);
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reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
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reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
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/* STATIC_ENT indicate that entry is static wouldn't
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@ -1021,6 +1021,10 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
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mt7530_write(priv, MT7530_PCR_P(port),
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PCR_MATRIX(dsa_user_ports(priv->ds)));
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/* Set to fallback mode for independent VLAN learning */
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mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
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MT7530_PORT_FALLBACK_MODE);
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return 0;
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}
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@ -1143,7 +1147,8 @@ mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
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break;
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}
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mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state);
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mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED),
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FID_PST(FID_BRIDGED, stp_state));
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}
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static int
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@ -1229,6 +1234,10 @@ mt7530_port_bridge_join(struct dsa_switch *ds, int port,
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PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
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priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
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/* Set to fallback mode for independent VLAN learning */
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mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
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MT7530_PORT_FALLBACK_MODE);
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mutex_unlock(&priv->reg_mutex);
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return 0;
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@ -1241,16 +1250,21 @@ mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
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bool all_user_ports_removed = true;
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int i;
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/* When a port is removed from the bridge, the port would be set up
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* back to the default as is at initial boot which is a VLAN-unaware
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* port.
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/* This is called after .port_bridge_leave when leaving a VLAN-aware
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* bridge. Don't set standalone ports to fallback mode.
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*/
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mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
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MT7530_PORT_MATRIX_MODE);
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if (dsa_to_port(ds, port)->bridge_dev)
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mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
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MT7530_PORT_FALLBACK_MODE);
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mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
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VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
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PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
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/* Set PVID to 0 */
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mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
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G0_PORT_VID_DEF);
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for (i = 0; i < MT7530_NUM_PORTS; i++) {
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if (dsa_is_user_port(ds, i) &&
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dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
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@ -1276,15 +1290,14 @@ mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
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struct mt7530_priv *priv = ds->priv;
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/* Trapped into security mode allows packet forwarding through VLAN
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* table lookup. CPU port is set to fallback mode to let untagged
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* frames pass through.
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* table lookup.
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*/
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if (dsa_is_cpu_port(ds, port))
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mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
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MT7530_PORT_FALLBACK_MODE);
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else
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if (dsa_is_user_port(ds, port)) {
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mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
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MT7530_PORT_SECURITY_MODE);
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mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
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G0_PORT_VID(priv->ports[port].pvid));
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}
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/* Set the port as a user port which is to be able to recognize VID
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* from incoming packets before fetching entry within the VLAN table.
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@ -1329,6 +1342,13 @@ mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
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PCR_MATRIX(BIT(MT7530_CPU_PORT)));
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priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
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/* When a port is removed from the bridge, the port would be set up
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* back to the default as is at initial boot which is a VLAN-unaware
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* port.
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*/
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mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
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MT7530_PORT_MATRIX_MODE);
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mutex_unlock(&priv->reg_mutex);
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}
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@ -1511,7 +1531,8 @@ mt7530_hw_vlan_add(struct mt7530_priv *priv,
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/* Validate the entry with independent learning, create egress tag per
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* VLAN and joining the port as one of the port members.
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*/
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val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID;
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val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) |
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VLAN_VALID;
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mt7530_write(priv, MT7530_VAWD1, val);
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/* Decide whether adding tag or not for those outgoing packets from the
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@ -1601,9 +1622,13 @@ mt7530_port_vlan_add(struct dsa_switch *ds, int port,
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mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add);
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if (pvid) {
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mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
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G0_PORT_VID(vlan->vid));
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priv->ports[port].pvid = vlan->vid;
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/* Only configure PVID if VLAN filtering is enabled */
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if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
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mt7530_rmw(priv, MT7530_PPBV1_P(port),
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G0_PORT_VID_MASK,
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G0_PORT_VID(vlan->vid));
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}
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mutex_unlock(&priv->reg_mutex);
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@ -1617,11 +1642,9 @@ mt7530_port_vlan_del(struct dsa_switch *ds, int port,
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{
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struct mt7530_hw_vlan_entry target_entry;
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struct mt7530_priv *priv = ds->priv;
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u16 pvid;
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mutex_lock(&priv->reg_mutex);
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pvid = priv->ports[port].pvid;
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mt7530_hw_vlan_entry_init(&target_entry, port, 0);
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mt7530_hw_vlan_update(priv, vlan->vid, &target_entry,
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mt7530_hw_vlan_del);
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@ -1629,11 +1652,12 @@ mt7530_port_vlan_del(struct dsa_switch *ds, int port,
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/* PVID is being restored to the default whenever the PVID port
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* is being removed from the VLAN.
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*/
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if (pvid == vlan->vid)
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pvid = G0_PORT_VID_DEF;
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if (priv->ports[port].pvid == vlan->vid) {
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priv->ports[port].pvid = G0_PORT_VID_DEF;
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mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
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G0_PORT_VID_DEF);
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}
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mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid);
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priv->ports[port].pvid = pvid;
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mutex_unlock(&priv->reg_mutex);
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@ -2046,6 +2070,7 @@ mt7530_setup(struct dsa_switch *ds)
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* as two netdev instances.
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*/
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dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent;
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ds->assisted_learning_on_cpu_port = true;
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ds->mtu_enforcement_ingress = true;
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if (priv->id == ID_MT7530) {
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@ -2116,6 +2141,9 @@ mt7530_setup(struct dsa_switch *ds)
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mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
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PCR_MATRIX_CLR);
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/* Disable learning by default on all ports */
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mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
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if (dsa_is_cpu_port(ds, i)) {
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ret = mt753x_cpu_port_enable(ds, i);
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if (ret)
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@ -2123,8 +2151,9 @@ mt7530_setup(struct dsa_switch *ds)
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} else {
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mt7530_port_disable(ds, i);
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/* Disable learning by default on all user ports */
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mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
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/* Set default PVID to 0 on all user ports */
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mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,
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G0_PORT_VID_DEF);
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}
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/* Enable consistent egress tag */
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mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
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@ -2281,6 +2310,9 @@ mt7531_setup(struct dsa_switch *ds)
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mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
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PCR_MATRIX_CLR);
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/* Disable learning by default on all ports */
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mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
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mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
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if (dsa_is_cpu_port(ds, i)) {
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@ -2290,8 +2322,9 @@ mt7531_setup(struct dsa_switch *ds)
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} else {
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mt7530_port_disable(ds, i);
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/* Disable learning by default on all user ports */
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mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
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/* Set default PVID to 0 on all user ports */
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mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,
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G0_PORT_VID_DEF);
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}
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/* Enable consistent egress tag */
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@ -2299,6 +2332,7 @@ mt7531_setup(struct dsa_switch *ds)
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PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
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}
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ds->assisted_learning_on_cpu_port = true;
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ds->mtu_enforcement_ingress = true;
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/* Flush the FDB table */
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@ -80,6 +80,7 @@ enum mt753x_bpdu_port_fw {
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#define STATIC_ENT 3
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#define MT7530_ATA2 0x78
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#define ATA2_IVL BIT(15)
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#define ATA2_FID(x) (((x) & 0x7) << 12)
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/* Register for address table write data */
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#define MT7530_ATWD 0x7c
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@ -148,11 +149,18 @@ enum mt7530_vlan_cmd {
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#define VTAG_EN BIT(28)
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/* VLAN Member Control */
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#define PORT_MEM(x) (((x) & 0xff) << 16)
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/* Filter ID */
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#define FID(x) (((x) & 0x7) << 1)
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/* VLAN Entry Valid */
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#define VLAN_VALID BIT(0)
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#define PORT_MEM_SHFT 16
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#define PORT_MEM_MASK 0xff
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enum mt7530_fid {
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FID_STANDALONE = 0,
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FID_BRIDGED = 1,
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};
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#define MT7530_VAWD2 0x98
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/* Egress Tag Control */
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#define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1))
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@ -179,8 +187,8 @@ enum mt7530_vlan_egress_attr {
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/* Register for port STP state control */
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#define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100))
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#define FID_PST(x) ((x) & 0x3)
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#define FID_PST_MASK FID_PST(0x3)
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#define FID_PST(fid, state) (((state) & 0x3) << ((fid) * 2))
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#define FID_PST_MASK(fid) FID_PST(fid, 0x3)
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enum mt7530_stp_state {
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MT7530_STP_DISABLED = 0,
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@ -247,7 +255,7 @@ enum mt7530_vlan_port_attr {
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#define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100))
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#define G0_PORT_VID(x) (((x) & 0xfff) << 0)
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#define G0_PORT_VID_MASK G0_PORT_VID(0xfff)
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#define G0_PORT_VID_DEF G0_PORT_VID(1)
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#define G0_PORT_VID_DEF G0_PORT_VID(0)
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/* Register for port MAC control register */
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#define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
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