clk:mxs: Fix bug on frequency divider
On drivers/clk/mxs/clk-frac.c, the function clk_frac_round_rate returned a bad result. The division before multiplication computes a wrong value ; the calculation is inverted to fix the problem. The second issue is that the exact rate have decimals and they are truncate. The consequence is that the function clk_frac_set_rate (which use the result of clk_frac_round_rate) computes a wrong value for the register (the rate generated can be closer to the desired rate). The correction is : if there is decimal to the result, it is rounded to the next larger integer. On drivers/clk/mxs/clk-frac.c, the function clk_frac_recalc_rate returned a bad result. The multiplication is made before the division to compute a correct value. Signed-off-by: Victorien Vedrine <victorien.vedrine@ophrys.net> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -41,11 +41,13 @@ static unsigned long clk_frac_recalc_rate(struct clk_hw *hw,
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{
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struct clk_frac *frac = to_clk_frac(hw);
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u32 div;
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u64 tmp_rate;
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div = readl_relaxed(frac->reg) >> frac->shift;
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div &= (1 << frac->width) - 1;
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return (parent_rate >> frac->width) * div;
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tmp_rate = (u64)parent_rate * div;
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return tmp_rate >> frac->width;
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}
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static long clk_frac_round_rate(struct clk_hw *hw, unsigned long rate,
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@ -54,7 +56,7 @@ static long clk_frac_round_rate(struct clk_hw *hw, unsigned long rate,
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struct clk_frac *frac = to_clk_frac(hw);
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unsigned long parent_rate = *prate;
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u32 div;
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u64 tmp;
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u64 tmp, tmp_rate, result;
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if (rate > parent_rate)
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return -EINVAL;
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@ -67,7 +69,11 @@ static long clk_frac_round_rate(struct clk_hw *hw, unsigned long rate,
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if (!div)
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return -EINVAL;
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return (parent_rate >> frac->width) * div;
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tmp_rate = (u64)parent_rate * div;
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result = tmp_rate >> frac->width;
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if ((result << frac->width) < tmp_rate)
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result += 1;
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return result;
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}
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static int clk_frac_set_rate(struct clk_hw *hw, unsigned long rate,
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