Add device tree nodes for
mt8173: - split USB SuperSpeed port in HighSpeed and SuperSpeed ports. - move USB phy clocks up in hierarchy to met new bindings description - move MDP nodes up in hierarchy to met new bindings description mt6797: - add basic SoC support - add clock driver - add power domain dt-bindings: - clean-up i2c binding description - add binding for mt2701 i2c node - add fallback compatible to scpsys binding description - add bindings description for mt7622 and mt6796 -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABAgAGBQJZPmpvAAoJELQ5Ylss8dND8NwQAI4LIEM7orrUJDBwnrXWRhXC O5UzuKG6S+cUqY4l/8z2pEcEjMxqcVY2NqtbUToJKc6ZXw08ho/VfMMUKjiAFj0C Xhtmis7G5srIIxd9cNuajPQ9zkUAkFNFJzQOirJTfZibyPbHcXuJW94/8qGztXKj QDsxWg4aPL35KPXZlhVAqya1hIXRlT49OaIH1qhCO0ZOpIWWH6Rj9c1lCmZA4B9o o9SmTg0PktG3r0LGT+2A9PQ0eukKKqGMSku+dUq5Uw/YxvHNO+qdyw0ZxUYyOrw2 aM/WKZeEPamfgVl5a6G+0iCxZbZqnwlIgjuHvKp87jNgEx+apUoBuweoSi+N4J/W a4efrgATcgseiMb8NNgj6AmvZr67rocG1ZOnMXazOUPj6hixMb2i3Zm7vm1wCezr gYV+dTUQwhyEIcJU3joju2xt4Ll7yWJlGvixeu8eFg5N/R6m12D49+tCgc93GA7v NXWDrX9/MdU9GwmuqvrAQAh/0DlmQkU32DxmQxqvPF+A0OzEzeYankLGlEe45wef CAsZMSO8DKmPfrKvEUR99aEthNkrzbg6Iiyl5EUWf1qNsXqXmaou2h+hoQaMsi4/ qCjQFO8F7bztJqCQAr+Ym95bFv2dpb2B+2S+7eb24V6OifxtWLwYDQywEJPekZft 7oOp24vJYzWl/dabwjmC =H12B -----END PGP SIGNATURE----- Merge tag 'v4.12-next-dts64' of https://github.com/mbgg/linux-mediatek into next/dt64 Add device tree nodes for mt8173: - split USB SuperSpeed port in HighSpeed and SuperSpeed ports. - move USB phy clocks up in hierarchy to met new bindings description - move MDP nodes up in hierarchy to met new bindings description mt6797: - add basic SoC support - add clock driver - add power domain dt-bindings: - clean-up i2c binding description - add binding for mt2701 i2c node - add fallback compatible to scpsys binding description - add bindings description for mt7622 and mt6796 * tag 'v4.12-next-dts64' of https://github.com/mbgg/linux-mediatek: dt-bindings: mediatek: add bindings for MediaTek MT7622 SoC arm64: dts: mt8173: Fix mdp device tree dt-bindings: i2c: Add Mediatek MT2701 i2c binding dt-bindings: i2c-mtk: Add mt7623 binding dt-bindings: i2c-mtk: Delete bindings dt-bindings: i2c-mt6577: Rename file to reflect bindings dt-bindings: mtk-sysirq: Correct bindings for supported SoCs arm64: dts: mediatek: add clk and scp nodes for MT6797 dt-bindings: mediatek: add MT6797 power dt-bindings arm64: dts: mediatek: add mt6797 support dt-bindings: mediatek: Add bindings for mediatek MT6797 Platform arm64: dts: mt8173: move clock from phy node into port nodes arm64: dts: mt8173: split usb SuperSpeed port into two ports Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
d8a4109634
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@ -12,6 +12,8 @@ compatible: Must contain one of
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"mediatek,mt6592"
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"mediatek,mt6755"
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"mediatek,mt6795"
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"mediatek,mt6797"
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"mediatek,mt7622"
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"mediatek,mt7623"
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"mediatek,mt8127"
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"mediatek,mt8135"
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@ -38,6 +40,12 @@ Supported boards:
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- Evaluation board for MT6795(Helio X10):
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Required root node properties:
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- compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
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- Evaluation board for MT6797(Helio X20):
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Required root node properties:
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- compatible = "mediatek,mt6797-evb", "mediatek,mt6797";
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- Reference board variant 1 for MT7622:
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Required root node properties:
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- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
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- Evaluation board for MT7623:
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Required root node properties:
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- compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
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@ -4,11 +4,11 @@ The Mediatek's I2C controller is used to interface with I2C devices.
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Required properties:
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- compatible: value should be either of the following.
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(a) "mediatek,mt6577-i2c", for i2c compatible with mt6577 i2c.
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(b) "mediatek,mt6589-i2c", for i2c compatible with mt6589 i2c.
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(c) "mediatek,mt8127-i2c", for i2c compatible with mt8127 i2c.
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(d) "mediatek,mt8135-i2c", for i2c compatible with mt8135 i2c.
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(e) "mediatek,mt8173-i2c", for i2c compatible with mt8173 i2c.
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"mediatek,mt2701-i2c", "mediatek,mt6577-i2c": for Mediatek mt2701
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"mediatek,mt6577-i2c": for i2c compatible with mt6577.
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"mediatek,mt6589-i2c": for i2c compatible with mt6589.
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"mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for i2c compatible with mt7623.
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"mediatek,mt8173-i2c": for i2c compatible with mt8173.
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- reg: physical base address of the controller and dma base, length of memory
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mapped region.
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- interrupts: interrupt number to the cpu.
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@ -1,21 +1,23 @@
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+Mediatek 65xx/67xx/81xx sysirq
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+Mediatek MT65xx/MT67xx/MT81xx sysirq
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Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI
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interrupt.
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Required properties:
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- compatible: should be one of:
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"mediatek,mt8173-sysirq"
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"mediatek,mt8135-sysirq"
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"mediatek,mt8127-sysirq"
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"mediatek,mt6795-sysirq"
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"mediatek,mt6755-sysirq"
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"mediatek,mt6592-sysirq"
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"mediatek,mt6589-sysirq"
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"mediatek,mt6582-sysirq"
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"mediatek,mt6580-sysirq"
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"mediatek,mt6577-sysirq"
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"mediatek,mt2701-sysirq"
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- compatible: should be
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"mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq": for MT8173
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"mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135
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"mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127
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"mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622
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"mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795
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"mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797
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"mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq": for MT6755
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"mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq": for MT6592
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"mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq": for MT6589
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"mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582
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"mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580
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"mediatek,mt6577-sysirq": for MT6577
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"mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
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- interrupt-parent: phandle of irq parent for sysirq. The parent must
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@ -8,6 +8,8 @@ Required properties:
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* "mediatek,mt6589-uart" for MT6589 compatible UARTS
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* "mediatek,mt6755-uart" for MT6755 compatible UARTS
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* "mediatek,mt6795-uart" for MT6795 compatible UARTS
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* "mediatek,mt6797-uart" for MT6797 compatible UARTS
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* "mediatek,mt7622-uart" for MT7622 compatible UARTS
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* "mediatek,mt7623-uart" for MT7623 compatible UARTS
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* "mediatek,mt8127-uart" for MT8127 compatible UARTS
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* "mediatek,mt8135-uart" for MT8135 compatible UARTS
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@ -9,11 +9,14 @@ domain control.
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The driver implements the Generic PM domain bindings described in
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power/power_domain.txt. It provides the power domains defined in
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include/dt-bindings/power/mt8173-power.h and mt2701-power.h.
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- include/dt-bindings/power/mt8173-power.h
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- include/dt-bindings/power/mt6797-power.h
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- include/dt-bindings/power/mt2701-power.h
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Required properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-scpsys"
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- "mediatek,mt6797-scpsys"
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- "mediatek,mt8173-scpsys"
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- #power-domain-cells: Must be 1
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- reg: Address range of the SCPSYS unit
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@ -22,6 +25,7 @@ Required properties:
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These are clocks which hardware needs to be
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enabled before enabling certain power domains.
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Required clocks for MT2701: "mm", "mfg", "ethif"
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Required clocks for MT6797: "mm", "mfg", "vdec"
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Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
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Optional properties:
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@ -1,5 +1,6 @@
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
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always := $(dtb-y)
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@ -0,0 +1,36 @@
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/*
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* Copyright (c) 2017 MediaTek Inc.
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* Author: Mars.C <mars.cheng@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
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*/
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/dts-v1/;
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#include "mt6797.dtsi"
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/ {
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model = "MediaTek MT6797 Evaluation Board";
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compatible = "mediatek,mt6797-evb", "mediatek,mt6797";
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aliases {
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serial0 = &uart0;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0 0x40000000 0 0x1e800000>;
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};
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chosen {};
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};
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&uart0 {
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status = "okay";
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};
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@ -0,0 +1,245 @@
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/*
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* Copyright (c) 2017 MediaTek Inc.
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* Author: Mars.C <mars.cheng@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
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||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
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*/
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#include <dt-bindings/clock/mt6797-clk.h>
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#include <dt-bindings/power/mt6797-power.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "mediatek,mt6797";
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interrupt-parent = <&sysirq>;
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#address-cells = <2>;
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#size-cells = <2>;
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x000>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x001>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x002>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x003>;
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};
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cpu4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x100>;
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};
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cpu5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x101>;
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};
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cpu6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x102>;
|
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};
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|
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cpu7: cpu@103 {
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device_type = "cpu";
|
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x103>;
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};
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cpu8: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
|
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enable-method = "psci";
|
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reg = <0x200>;
|
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};
|
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|
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cpu9: cpu@201 {
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device_type = "cpu";
|
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compatible = "arm,cortex-a72";
|
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enable-method = "psci";
|
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reg = <0x201>;
|
||||
};
|
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};
|
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|
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clk26m: oscillator@0 {
|
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compatible = "fixed-clock";
|
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#clock-cells = <0>;
|
||||
clock-frequency = <26000000>;
|
||||
clock-output-names = "clk26m";
|
||||
};
|
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|
||||
clk32k: oscillator@1 {
|
||||
compatible = "fixed-clock";
|
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#clock-cells = <0>;
|
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clock-frequency = <32000>;
|
||||
clock-output-names = "clk32k";
|
||||
};
|
||||
|
||||
timer {
|
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compatible = "arm,armv8-timer";
|
||||
interrupt-parent = <&gic>;
|
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
topckgen: topckgen@10000000 {
|
||||
compatible = "mediatek,mt6797-topckgen";
|
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reg = <0 0x10000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
infrasys: infracfg_ao@10001000 {
|
||||
compatible = "mediatek,mt6797-infracfg", "syscon";
|
||||
reg = <0 0x10001000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
scpsys: scpsys@10006000 {
|
||||
compatible = "mediatek,mt6797-scpsys";
|
||||
#power-domain-cells = <1>;
|
||||
reg = <0 0x10006000 0 0x1000>;
|
||||
clocks = <&topckgen CLK_TOP_MUX_MFG>,
|
||||
<&topckgen CLK_TOP_MUX_MM>,
|
||||
<&topckgen CLK_TOP_MUX_VDEC>;
|
||||
clock-names = "mfg", "mm", "vdec";
|
||||
infracfg = <&infrasys>;
|
||||
};
|
||||
|
||||
apmixedsys: apmixed@1000c000 {
|
||||
compatible = "mediatek,mt6797-apmixedsys";
|
||||
reg = <0 0x1000c000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sysirq: intpol-controller@10200620 {
|
||||
compatible = "mediatek,mt6797-sysirq",
|
||||
"mediatek,mt6577-sysirq";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-parent = <&gic>;
|
||||
reg = <0 0x10220620 0 0x20>,
|
||||
<0 0x10220690 0 0x10>;
|
||||
};
|
||||
|
||||
uart0: serial@11002000 {
|
||||
compatible = "mediatek,mt6797-uart",
|
||||
"mediatek,mt6577-uart";
|
||||
reg = <0 0x11002000 0 0x400>;
|
||||
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infrasys CLK_INFRA_UART0>,
|
||||
<&infrasys CLK_INFRA_AP_DMA>;
|
||||
clock-names = "baud", "bus";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@11003000 {
|
||||
compatible = "mediatek,mt6797-uart",
|
||||
"mediatek,mt6577-uart";
|
||||
reg = <0 0x11003000 0 0x400>;
|
||||
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infrasys CLK_INFRA_UART1>,
|
||||
<&infrasys CLK_INFRA_AP_DMA>;
|
||||
clock-names = "baud", "bus";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@11004000 {
|
||||
compatible = "mediatek,mt6797-uart",
|
||||
"mediatek,mt6577-uart";
|
||||
reg = <0 0x11004000 0 0x400>;
|
||||
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infrasys CLK_INFRA_UART2>,
|
||||
<&infrasys CLK_INFRA_AP_DMA>;
|
||||
clock-names = "baud", "bus";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@11005000 {
|
||||
compatible = "mediatek,mt6797-uart",
|
||||
"mediatek,mt6577-uart";
|
||||
reg = <0 0x11005000 0 0x400>;
|
||||
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infrasys CLK_INFRA_UART3>,
|
||||
<&infrasys CLK_INFRA_AP_DMA>;
|
||||
clock-names = "baud", "bus";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmsys: mmsys_config@14000000 {
|
||||
compatible = "mediatek,mt6797-mmsys", "syscon";
|
||||
reg = <0 0x14000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
imgsys: imgsys_config@15000000 {
|
||||
compatible = "mediatek,mt6797-imgsys", "syscon";
|
||||
reg = <0 0x15000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
vdecsys: vdec_gcon@16000000 {
|
||||
compatible = "mediatek,mt6797-vdecsys", "syscon";
|
||||
reg = <0 0x16000000 0 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
vencsys: venc_gcon@17000000 {
|
||||
compatible = "mediatek,mt6797-vencsys", "syscon";
|
||||
reg = <0 0x17000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@19000000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
reg = <0 0x19000000 0 0x10000>, /* GICD */
|
||||
<0 0x19200000 0 0x200000>, /* GICR */
|
||||
<0 0x10240000 0 0x2000>; /* GICC */
|
||||
};
|
||||
};
|
||||
|
|
@ -731,8 +731,9 @@ ssusb: usb@11271000 {
|
|||
<0 0x11280700 0 0x0100>;
|
||||
reg-names = "mac", "ippc";
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
|
||||
phys = <&phy_port0 PHY_TYPE_USB3>,
|
||||
<&phy_port1 PHY_TYPE_USB2>;
|
||||
phys = <&u2port0 PHY_TYPE_USB2>,
|
||||
<&u3port0 PHY_TYPE_USB3>,
|
||||
<&u2port1 PHY_TYPE_USB2>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
|
||||
clocks = <&topckgen CLK_TOP_USB30_SEL>,
|
||||
<&clk26m>,
|
||||
|
|
@ -763,21 +764,31 @@ usb_host: xhci@11270000 {
|
|||
u3phy: usb-phy@11290000 {
|
||||
compatible = "mediatek,mt8173-u3phy";
|
||||
reg = <0 0x11290000 0 0x800>;
|
||||
clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
|
||||
clock-names = "u3phya_ref";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
status = "okay";
|
||||
|
||||
phy_port0: port@11290800 {
|
||||
reg = <0 0x11290800 0 0x800>;
|
||||
u2port0: usb-phy@11290800 {
|
||||
reg = <0 0x11290800 0 0x100>;
|
||||
clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
|
||||
clock-names = "ref";
|
||||
#phy-cells = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
phy_port1: port@11291000 {
|
||||
reg = <0 0x11291000 0 0x800>;
|
||||
u3port0: usb-phy@11290900 {
|
||||
reg = <0 0x11290900 0 0x700>;
|
||||
clocks = <&clk26m>;
|
||||
clock-names = "ref";
|
||||
#phy-cells = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
u2port1: usb-phy@11291000 {
|
||||
reg = <0 0x11291000 0 0x100>;
|
||||
clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
|
||||
clock-names = "ref";
|
||||
#phy-cells = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -792,80 +803,74 @@ mmsys: clock-controller@14000000 {
|
|||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
mdp {
|
||||
compatible = "mediatek,mt8173-mdp";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
mdp_rdma0: rdma@14001000 {
|
||||
compatible = "mediatek,mt8173-mdp-rdma",
|
||||
"mediatek,mt8173-mdp";
|
||||
reg = <0 0x14001000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_MDP_RDMA0>,
|
||||
<&mmsys CLK_MM_MUTEX_32K>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
iommus = <&iommu M4U_PORT_MDP_RDMA0>;
|
||||
mediatek,larb = <&larb0>;
|
||||
mediatek,vpu = <&vpu>;
|
||||
};
|
||||
|
||||
mdp_rdma0: rdma@14001000 {
|
||||
compatible = "mediatek,mt8173-mdp-rdma";
|
||||
reg = <0 0x14001000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_MDP_RDMA0>,
|
||||
<&mmsys CLK_MM_MUTEX_32K>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
iommus = <&iommu M4U_PORT_MDP_RDMA0>;
|
||||
mediatek,larb = <&larb0>;
|
||||
};
|
||||
mdp_rdma1: rdma@14002000 {
|
||||
compatible = "mediatek,mt8173-mdp-rdma";
|
||||
reg = <0 0x14002000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_MDP_RDMA1>,
|
||||
<&mmsys CLK_MM_MUTEX_32K>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
iommus = <&iommu M4U_PORT_MDP_RDMA1>;
|
||||
mediatek,larb = <&larb4>;
|
||||
};
|
||||
|
||||
mdp_rdma1: rdma@14002000 {
|
||||
compatible = "mediatek,mt8173-mdp-rdma";
|
||||
reg = <0 0x14002000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_MDP_RDMA1>,
|
||||
<&mmsys CLK_MM_MUTEX_32K>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
iommus = <&iommu M4U_PORT_MDP_RDMA1>;
|
||||
mediatek,larb = <&larb4>;
|
||||
};
|
||||
mdp_rsz0: rsz@14003000 {
|
||||
compatible = "mediatek,mt8173-mdp-rsz";
|
||||
reg = <0 0x14003000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_MDP_RSZ0>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
};
|
||||
|
||||
mdp_rsz0: rsz@14003000 {
|
||||
compatible = "mediatek,mt8173-mdp-rsz";
|
||||
reg = <0 0x14003000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_MDP_RSZ0>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
};
|
||||
mdp_rsz1: rsz@14004000 {
|
||||
compatible = "mediatek,mt8173-mdp-rsz";
|
||||
reg = <0 0x14004000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_MDP_RSZ1>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
};
|
||||
|
||||
mdp_rsz1: rsz@14004000 {
|
||||
compatible = "mediatek,mt8173-mdp-rsz";
|
||||
reg = <0 0x14004000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_MDP_RSZ1>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
};
|
||||
mdp_rsz2: rsz@14005000 {
|
||||
compatible = "mediatek,mt8173-mdp-rsz";
|
||||
reg = <0 0x14005000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_MDP_RSZ2>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
};
|
||||
|
||||
mdp_rsz2: rsz@14005000 {
|
||||
compatible = "mediatek,mt8173-mdp-rsz";
|
||||
reg = <0 0x14005000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_MDP_RSZ2>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
};
|
||||
mdp_wdma0: wdma@14006000 {
|
||||
compatible = "mediatek,mt8173-mdp-wdma";
|
||||
reg = <0 0x14006000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_MDP_WDMA>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
iommus = <&iommu M4U_PORT_MDP_WDMA>;
|
||||
mediatek,larb = <&larb0>;
|
||||
};
|
||||
|
||||
mdp_wdma0: wdma@14006000 {
|
||||
compatible = "mediatek,mt8173-mdp-wdma";
|
||||
reg = <0 0x14006000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_MDP_WDMA>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
iommus = <&iommu M4U_PORT_MDP_WDMA>;
|
||||
mediatek,larb = <&larb0>;
|
||||
};
|
||||
mdp_wrot0: wrot@14007000 {
|
||||
compatible = "mediatek,mt8173-mdp-wrot";
|
||||
reg = <0 0x14007000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_MDP_WROT0>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
iommus = <&iommu M4U_PORT_MDP_WROT0>;
|
||||
mediatek,larb = <&larb0>;
|
||||
};
|
||||
|
||||
mdp_wrot0: wrot@14007000 {
|
||||
compatible = "mediatek,mt8173-mdp-wrot";
|
||||
reg = <0 0x14007000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_MDP_WROT0>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
iommus = <&iommu M4U_PORT_MDP_WROT0>;
|
||||
mediatek,larb = <&larb0>;
|
||||
};
|
||||
|
||||
mdp_wrot1: wrot@14008000 {
|
||||
compatible = "mediatek,mt8173-mdp-wrot";
|
||||
reg = <0 0x14008000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_MDP_WROT1>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
iommus = <&iommu M4U_PORT_MDP_WROT1>;
|
||||
mediatek,larb = <&larb4>;
|
||||
};
|
||||
mdp_wrot1: wrot@14008000 {
|
||||
compatible = "mediatek,mt8173-mdp-wrot";
|
||||
reg = <0 0x14008000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_MDP_WROT1>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
iommus = <&iommu M4U_PORT_MDP_WROT1>;
|
||||
mediatek,larb = <&larb4>;
|
||||
};
|
||||
|
||||
ovl0: ovl@1400c000 {
|
||||
|
|
|
|||
Loading…
Reference in New Issue