net/mlx4: Query RoCE support
Query the RoCE support from firmware using the appropriate firmware commands. Downstream patches will read these capabilities and act accordingly. Signed-off-by: Moni Shoua <monis@mellanox.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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@ -157,6 +157,7 @@ static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
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[29] = "802.1ad offload support",
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[31] = "Modifying loopback source checks using UPDATE_QP support",
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[32] = "Loopback source checks support",
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[33] = "RoCEv2 support"
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};
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int i;
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@ -626,6 +627,8 @@ int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port,
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return err;
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}
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static void disable_unsupported_roce_caps(void *buf);
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int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
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{
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struct mlx4_cmd_mailbox *mailbox;
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@ -738,6 +741,8 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
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if (err)
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goto out;
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if (mlx4_is_mfunc(dev))
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disable_unsupported_roce_caps(outbox);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
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dev_cap->reserved_qps = 1 << (field & 0xf);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
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@ -905,6 +910,8 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
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dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
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MLX4_GET(dev_cap->bmme_flags, outbox,
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QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
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if (dev_cap->bmme_flags & MLX4_FLAG_ROCE_V1_V2)
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dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ROCE_V1_V2;
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if (dev_cap->bmme_flags & MLX4_FLAG_PORT_REMAP)
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dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_REMAP;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
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@ -1160,6 +1167,7 @@ int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
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if (err)
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return err;
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disable_unsupported_roce_caps(outbox->buf);
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/* add port mng change event capability and disable mw type 1
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* unconditionally to slaves
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*/
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@ -1257,6 +1265,21 @@ int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
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return 0;
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}
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static void disable_unsupported_roce_caps(void *buf)
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{
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u32 flags;
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MLX4_GET(flags, buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
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flags &= ~(1UL << 31);
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MLX4_PUT(buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
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MLX4_GET(flags, buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
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flags &= ~(1UL << 24);
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MLX4_PUT(buf, flags, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
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MLX4_GET(flags, buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
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flags &= ~(MLX4_FLAG_ROCE_V1_V2);
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MLX4_PUT(buf, flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
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}
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int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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@ -216,6 +216,7 @@ enum {
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MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30,
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MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31,
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MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1ULL << 32,
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MLX4_DEV_CAP_FLAG2_ROCE_V1_V2 = 1ULL << 33,
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};
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enum {
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@ -267,12 +268,14 @@ enum {
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MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
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MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
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MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
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MLX4_BMME_FLAG_ROCE_V1_V2 = 1 << 19,
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MLX4_BMME_FLAG_PORT_REMAP = 1 << 24,
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MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28,
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};
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enum {
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MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP
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MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP,
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MLX4_FLAG_ROCE_V1_V2 = MLX4_BMME_FLAG_ROCE_V1_V2
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};
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enum mlx4_event {
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@ -980,9 +983,10 @@ struct mlx4_mad_ifc {
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if ((type) == (dev)->caps.port_mask[(port)])
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#define mlx4_foreach_ib_transport_port(port, dev) \
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for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
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for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
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if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
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((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
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((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) || \
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((dev)->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2))
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#define MLX4_INVALID_SLAVE_ID 0xFF
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#define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1)
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