ARM: re-implement physical address space switching
Re-implement the physical address space switching to be architecturally compliant. This involves flushing the caches, disabling the MMU, and only then updating the page tables. Once that is complete, the system can be brought back up again. Since we disable the MMU, we need to do the update in assembly code. Luckily, the entries which need updating are fairly trivial, and are all setup by the early assembly code. We can merely adjust each entry by the delta required. Not only does this fix the code to be architecturally compliant, but it fixes a couple of bugs too: 1. The original code would only ever update the first L2 entry covering a fraction of the kernel; the remainder were left untouched. 2. The L2 entries covering the DTB blob were likewise untouched. This solution fixes up all entries. Tested-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
parent
c0b759d87e
commit
d8dc7fbd53
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@ -624,6 +624,10 @@ config ARM_LPAE
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If unsure, say N.
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config ARM_PV_FIXUP
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def_bool y
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depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE
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config ARCH_PHYS_ADDR_T_64BIT
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def_bool ARM_LPAE
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@ -18,6 +18,7 @@ obj-$(CONFIG_MODULES) += proc-syms.o
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obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o
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obj-$(CONFIG_HIGHMEM) += highmem.o
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obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
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obj-$(CONFIG_ARM_PV_FIXUP) += pv-fixup-asm.o
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obj-$(CONFIG_CPU_ABRT_NOMMU) += abort-nommu.o
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obj-$(CONFIG_CPU_ABRT_EV4) += abort-ev4.o
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@ -1387,7 +1387,11 @@ static void __init map_lowmem(void)
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}
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}
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#if defined(CONFIG_ARM_LPAE) && defined(CONFIG_ARM_PATCH_PHYS_VIRT)
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#ifdef CONFIG_ARM_PV_FIXUP
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extern unsigned long __atags_pointer;
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typedef void pgtables_remap(long long offset, unsigned long pgd, void *bdata);
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pgtables_remap lpae_pgtables_remap_asm;
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/*
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* early_paging_init() recreates boot time page table setup, allowing machines
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* to switch over to a high (>4G) address space on LPAE systems
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@ -1395,35 +1399,30 @@ static void __init map_lowmem(void)
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void __init early_paging_init(const struct machine_desc *mdesc,
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struct proc_info_list *procinfo)
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{
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pmdval_t pmdprot = procinfo->__cpu_mm_mmu_flags;
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unsigned long map_start, map_end;
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pgtables_remap *lpae_pgtables_remap;
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unsigned long pa_pgd;
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unsigned int cr, ttbcr;
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long long offset;
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pgd_t *pgd0, *pgdk;
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pud_t *pud0, *pudk, *pud_start;
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pmd_t *pmd0, *pmdk;
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phys_addr_t phys;
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int i;
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void *boot_data;
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if (!mdesc->pv_fixup)
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return;
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/* remap kernel code and data */
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map_start = init_mm.start_code & PMD_MASK;
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map_end = ALIGN(init_mm.brk, PMD_SIZE);
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/* get a handle on things... */
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pgd0 = pgd_offset_k(0);
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pud_start = pud0 = pud_offset(pgd0, 0);
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pmd0 = pmd_offset(pud0, 0);
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pgdk = pgd_offset_k(map_start);
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pudk = pud_offset(pgdk, map_start);
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pmdk = pmd_offset(pudk, map_start);
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offset = mdesc->pv_fixup();
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if (offset == 0)
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return;
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/*
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* Get the address of the remap function in the 1:1 identity
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* mapping setup by the early page table assembly code. We
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* must get this prior to the pv update. The following barrier
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* ensures that this is complete before we fixup any P:V offsets.
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*/
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lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm);
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pa_pgd = __pa(swapper_pg_dir);
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boot_data = __va(__atags_pointer);
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barrier();
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pr_info("Switching physical address space to 0x%08llx\n",
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(u64)PHYS_OFFSET + offset);
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@ -1436,75 +1435,32 @@ void __init early_paging_init(const struct machine_desc *mdesc,
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(&__pv_table_end - &__pv_table_begin) << 2);
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/*
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* Cache cleaning operations for self-modifying code
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* We should clean the entries by MVA but running a
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* for loop over every pv_table entry pointer would
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* just complicate the code.
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*/
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flush_cache_louis();
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dsb(ishst);
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isb();
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/*
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* FIXME: This code is not architecturally compliant: we modify
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* the mappings in-place, indeed while they are in use by this
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* very same code. This may lead to unpredictable behaviour of
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* the CPU.
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*
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* Even modifying the mappings in a separate page table does
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* not resolve this.
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*
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* The architecture strongly recommends that when a mapping is
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* changed, that it is changed by first going via an invalid
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* mapping and back to the new mapping. This is to ensure that
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* no TLB conflicts (caused by the TLB having more than one TLB
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* entry match a translation) can occur. However, doing that
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* here will result in unmapping the code we are running.
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*/
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pr_warn("WARNING: unsafe modification of in-place page tables - tainting kernel\n");
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add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
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/*
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* Remap level 1 table. This changes the physical addresses
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* used to refer to the level 2 page tables to the high
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* physical address alias, leaving everything else the same.
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*/
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for (i = 0; i < PTRS_PER_PGD; pud0++, i++) {
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set_pud(pud0,
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__pud(__pa(pmd0) | PMD_TYPE_TABLE | L_PGD_SWAPPER));
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pmd0 += PTRS_PER_PMD;
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}
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/*
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* Remap the level 2 table, pointing the mappings at the high
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* physical address alias of these pages.
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*/
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phys = __pa(map_start);
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do {
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*pmdk++ = __pmd(phys | pmdprot);
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phys += PMD_SIZE;
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} while (phys < map_end);
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/*
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* Ensure that the above updates are flushed out of the cache.
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* This is not strictly correct; on a system where the caches
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* are coherent with each other, but the MMU page table walks
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* may not be coherent, flush_cache_all() may be a no-op, and
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* this will fail.
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* We changing not only the virtual to physical mapping, but also
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* the physical addresses used to access memory. We need to flush
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* all levels of cache in the system with caching disabled to
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* ensure that all data is written back, and nothing is prefetched
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* into the caches. We also need to prevent the TLB walkers
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* allocating into the caches too. Note that this is ARMv7 LPAE
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* specific.
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*/
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cr = get_cr();
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set_cr(cr & ~(CR_I | CR_C));
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asm("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr));
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asm volatile("mcr p15, 0, %0, c2, c0, 2"
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: : "r" (ttbcr & ~(3 << 8 | 3 << 10)));
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flush_cache_all();
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/*
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* Re-write the TTBR values to point them at the high physical
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* alias of the page tables. We expect __va() will work on
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* cpu_get_pgd(), which returns the value of TTBR0.
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* Fixup the page tables - this must be in the idmap region as
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* we need to disable the MMU to do this safely, and hence it
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* needs to be assembly. It's fairly simple, as we're using the
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* temporary tables setup by the initial assembly code.
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*/
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cpu_switch_mm(pgd0, &init_mm);
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cpu_set_ttbr(1, __pa(pgd0) + TTBR1_OFFSET);
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lpae_pgtables_remap(offset, pa_pgd, boot_data);
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/* Finally flush any stale TLB values. */
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local_flush_bp_all();
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local_flush_tlb_all();
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/* Re-enable the caches and cacheable TLB walks */
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asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr));
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set_cr(cr);
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}
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#else
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@ -0,0 +1,88 @@
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/*
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* Copyright (C) 2015 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This assembly is required to safely remap the physical address space
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* for Keystone 2
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*/
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/cp15.h>
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#include <asm/memory.h>
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#include <asm/pgtable.h>
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.section ".idmap.text", "ax"
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#define L1_ORDER 3
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#define L2_ORDER 3
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ENTRY(lpae_pgtables_remap_asm)
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stmfd sp!, {r4-r8, lr}
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mrc p15, 0, r8, c1, c0, 0 @ read control reg
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bic ip, r8, #CR_M @ disable caches and MMU
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mcr p15, 0, ip, c1, c0, 0
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dsb
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isb
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/* Update level 2 entries covering the kernel */
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ldr r6, =(_end - 1)
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add r7, r2, #0x1000
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add r6, r7, r6, lsr #SECTION_SHIFT - L2_ORDER
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add r7, r7, #PAGE_OFFSET >> (SECTION_SHIFT - L2_ORDER)
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1: ldrd r4, [r7]
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adds r4, r4, r0
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adc r5, r5, r1
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strd r4, [r7], #1 << L2_ORDER
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cmp r7, r6
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bls 1b
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/* Update level 2 entries for the boot data */
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add r7, r2, #0x1000
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add r7, r7, r3, lsr #SECTION_SHIFT - L2_ORDER
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bic r7, r7, #(1 << L2_ORDER) - 1
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ldrd r4, [r7]
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adds r4, r4, r0
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adc r5, r5, r1
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strd r4, [r7], #1 << L2_ORDER
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ldrd r4, [r7]
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adds r4, r4, r0
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adc r5, r5, r1
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strd r4, [r7]
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/* Update level 1 entries */
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mov r6, #4
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mov r7, r2
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2: ldrd r4, [r7]
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adds r4, r4, r0
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adc r5, r5, r1
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strd r4, [r7], #1 << L1_ORDER
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subs r6, r6, #1
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bne 2b
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mrrc p15, 0, r4, r5, c2 @ read TTBR0
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adds r4, r4, r0 @ update physical address
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adc r5, r5, r1
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mcrr p15, 0, r4, r5, c2 @ write back TTBR0
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mrrc p15, 1, r4, r5, c2 @ read TTBR1
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adds r4, r4, r0 @ update physical address
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adc r5, r5, r1
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mcrr p15, 1, r4, r5, c2 @ write back TTBR1
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dsb
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mov ip, #0
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mcr p15, 0, ip, c7, c5, 0 @ I+BTB cache invalidate
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mcr p15, 0, ip, c8, c7, 0 @ local_flush_tlb_all()
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dsb
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isb
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mcr p15, 0, r8, c1, c0, 0 @ re-enable MMU
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dsb
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isb
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ldmfd sp!, {r4-r8, pc}
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ENDPROC(lpae_pgtables_remap_asm)
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