Merge branch 'pci/host-hisi' into next
* pci/host-hisi: PCI: generic: Call pci_fixup_irqs() only on ARM PCI: Disable MSI for HiSilicon Hip06/Hip07 Root Ports PCI: hisi: Rename config space accessors to remove "acpi" PCI: hisi: Add DT almost-ECAM support for Hip06/Hip07 host controllers PCI: hisi: Use of_device_get_match_data() to simplify probe Conflicts: drivers/pci/dwc/pcie-hisi.c
This commit is contained in:
Bjorn Helgaas
commit
d952097158
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@ -42,3 +42,40 @@ Hip05 Example (note that Hip06 is the same except compatible):
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0x0 0 0 4 &mbigen_pcie 4 13>;
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status = "ok";
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};
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HiSilicon Hip06/Hip07 PCIe host bridge DT (almost-ECAM) description.
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The properties and their meanings are identical to those described in
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host-generic-pci.txt except as listed below.
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Properties of the host controller node that differ from
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host-generic-pci.txt:
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- compatible : Must be "hisilicon,pcie-almost-ecam"
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- reg : Two entries: First the ECAM configuration space for any
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other bus underneath the root bus. Second, the base
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and size of the HiSilicon host bridge registers include
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the RC's own config space.
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Example:
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pcie0: pcie@a0090000 {
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compatible = "hisilicon,pcie-almost-ecam";
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reg = <0 0xb0000000 0 0x2000000>, /* ECAM configuration space */
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<0 0xa0090000 0 0x10000>; /* host bridge registers */
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bus-range = <0 31>;
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msi-map = <0x0000 &its_dsa 0x0000 0x2000>;
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msi-map-mask = <0xffff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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dma-coherent;
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ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 0x5ff0000
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0x01000000 0 0 0 0xb7ff0000 0 0x10000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4
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0x0 0 0 2 &mbigen_pcie0 650 4
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0x0 0 0 3 &mbigen_pcie0 650 4
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0x0 0 0 4 &mbigen_pcie0 650 4>;
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status = "ok";
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};
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@ -24,10 +24,10 @@
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#include <linux/regmap.h>
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#include "../pci.h"
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#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
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#if defined(CONFIG_PCI_HISI) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
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static int hisi_pcie_acpi_rd_conf(struct pci_bus *bus, u32 devfn, int where,
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int size, u32 *val)
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static int hisi_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
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int size, u32 *val)
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{
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struct pci_config_window *cfg = bus->sysdata;
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int dev = PCI_SLOT(devfn);
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@ -44,8 +44,8 @@ static int hisi_pcie_acpi_rd_conf(struct pci_bus *bus, u32 devfn, int where,
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return pci_generic_config_read(bus, devfn, where, size, val);
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}
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static int hisi_pcie_acpi_wr_conf(struct pci_bus *bus, u32 devfn,
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int where, int size, u32 val)
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static int hisi_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
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int where, int size, u32 val)
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{
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struct pci_config_window *cfg = bus->sysdata;
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int dev = PCI_SLOT(devfn);
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@ -74,6 +74,8 @@ static void __iomem *hisi_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
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return pci_ecam_map_bus(bus, devfn, where);
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}
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#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
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static int hisi_pcie_init(struct pci_config_window *cfg)
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{
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struct device *dev = cfg->parent;
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@ -110,8 +112,8 @@ struct pci_ecam_ops hisi_pcie_ops = {
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.init = hisi_pcie_init,
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.pci_ops = {
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.map_bus = hisi_pcie_map_bus,
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.read = hisi_pcie_acpi_rd_conf,
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.write = hisi_pcie_acpi_wr_conf,
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.read = hisi_pcie_rd_conf,
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.write = hisi_pcie_wr_conf,
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}
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};
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@ -139,7 +141,7 @@ struct hisi_pcie {
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struct dw_pcie *pci;
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struct regmap *subctrl;
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u32 port_id;
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struct pcie_soc_ops *soc_ops;
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const struct pcie_soc_ops *soc_ops;
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};
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/* HipXX PCIe host only supports 32-bit config access */
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@ -265,7 +267,6 @@ static int hisi_pcie_probe(struct platform_device *pdev)
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struct device *dev = &pdev->dev;
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struct dw_pcie *pci;
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struct hisi_pcie *hisi_pcie;
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const struct of_device_id *match;
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struct resource *reg;
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struct device_driver *driver;
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int ret;
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@ -283,11 +284,10 @@ static int hisi_pcie_probe(struct platform_device *pdev)
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driver = dev->driver;
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match = of_match_device(driver->of_match_table, dev);
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hisi_pcie->soc_ops = (struct pcie_soc_ops *) match->data;
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hisi_pcie->soc_ops = of_device_get_match_data(dev);
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hisi_pcie->subctrl =
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syscon_regmap_lookup_by_compatible("hisilicon,pcie-sas-subctrl");
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syscon_regmap_lookup_by_compatible("hisilicon,pcie-sas-subctrl");
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if (IS_ERR(hisi_pcie->subctrl)) {
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dev_err(dev, "cannot get subctrl base\n");
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return PTR_ERR(hisi_pcie->subctrl);
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@ -336,4 +336,62 @@ static struct platform_driver hisi_pcie_driver = {
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};
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builtin_platform_driver(hisi_pcie_driver);
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static int hisi_pcie_almost_ecam_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct pci_ecam_ops *ops;
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ops = (struct pci_ecam_ops *)of_device_get_match_data(dev);
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return pci_host_common_probe(pdev, ops);
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}
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static int hisi_pcie_platform_init(struct pci_config_window *cfg)
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{
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struct device *dev = cfg->parent;
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struct platform_device *pdev = to_platform_device(dev);
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struct resource *res;
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void __iomem *reg_base;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!res) {
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dev_err(dev, "missing \"reg[1]\"property\n");
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return -EINVAL;
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}
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reg_base = devm_ioremap(dev, res->start, resource_size(res));
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if (!reg_base)
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return -ENOMEM;
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cfg->priv = reg_base;
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return 0;
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}
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struct pci_ecam_ops hisi_pcie_platform_ops = {
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.bus_shift = 20,
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.init = hisi_pcie_platform_init,
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.pci_ops = {
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.map_bus = hisi_pcie_map_bus,
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.read = hisi_pcie_rd_conf,
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.write = hisi_pcie_wr_conf,
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}
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};
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static const struct of_device_id hisi_pcie_almost_ecam_of_match[] = {
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{
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.compatible = "hisilicon,pcie-almost-ecam",
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.data = (void *) &hisi_pcie_platform_ops,
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},
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{},
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};
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static struct platform_driver hisi_pcie_almost_ecam_driver = {
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.probe = hisi_pcie_almost_ecam_probe,
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.driver = {
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.name = "hisi-pcie-almost-ecam",
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.of_match_table = hisi_pcie_almost_ecam_of_match,
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},
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};
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builtin_platform_driver(hisi_pcie_almost_ecam_driver);
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#endif
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#endif
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@ -145,7 +145,9 @@ int pci_host_common_probe(struct platform_device *pdev,
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return -ENODEV;
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}
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#ifdef CONFIG_ARM
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pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
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#endif
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/*
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* We insert PCI resources into the iomem_resource and
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@ -1634,6 +1634,7 @@ static void quirk_pcie_mch(struct pci_dev *pdev)
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, quirk_pcie_mch);
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/*
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@ -2516,6 +2516,8 @@
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#define PCI_DEVICE_ID_KORENIX_JETCARDF2 0x1700
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#define PCI_DEVICE_ID_KORENIX_JETCARDF3 0x17ff
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#define PCI_VENDOR_ID_HUAWEI 0x19e5
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#define PCI_VENDOR_ID_NETRONOME 0x19ee
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#define PCI_DEVICE_ID_NETRONOME_NFP3200 0x3200
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#define PCI_DEVICE_ID_NETRONOME_NFP3240 0x3240
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