Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull missed timer updates from Thomas Gleixner: "This is a branch which got forgotten during the merge window, but it contains only fixes and hardware enablement. No fundamental changes. - Various fixes for the imx-tpm clocksource driver - A new timer driver for the NCPM7xx SoC family" * 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: clocksource/drivers/imx-tpm: Add different counter width support clocksource/drivers/imx-tpm: Correct some registers operation flow clocksource/drivers/imx-tpm: Fix typo of clock name dt-bindings: timer: tpm: fix typo of clock name clocksource/drivers/npcm: Add NPCM7xx timer driver dt-binding: timer: document NPCM7xx timer DT bindings
This commit is contained in:
Linus Torvalds
commit
d95c884439
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@ -0,0 +1,21 @@
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Nuvoton NPCM7xx timer
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Nuvoton NPCM7xx have three timer modules, each timer module provides five 24-bit
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timer counters.
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Required properties:
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- compatible : "nuvoton,npcm750-timer" for Poleg NPCM750.
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- reg : Offset and length of the register set for the device.
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- interrupts : Contain the timer interrupt with flags for
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falling edge.
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- clocks : phandle of timer reference clock (usually a 25 MHz clock).
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Example:
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timer@f0008000 {
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compatible = "nuvoton,npcm750-timer";
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf0008000 0x50>;
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clocks = <&clk NPCM7XX_CLK_TIMER>;
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};
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@ -15,7 +15,7 @@ Required properties:
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- interrupts : Should be the clock event device interrupt.
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- clocks : The clocks provided by the SoC to drive the timer, must contain
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an entry for each entry in clock-names.
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- clock-names : Must include the following entries: "igp" and "per".
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- clock-names : Must include the following entries: "ipg" and "per".
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Example:
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tpm5: tpm@40260000 {
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@ -133,6 +133,14 @@ config VT8500_TIMER
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help
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Enables support for the VT8500 driver.
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config NPCM7XX_TIMER
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bool "NPCM7xx timer driver" if COMPILE_TEST
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depends on HAS_IOMEM
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select CLKSRC_MMIO
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help
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Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
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While TIMER0 serves as clockevent and TIMER1 serves as clocksource.
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config CADENCE_TTC_TIMER
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bool "Cadence TTC timer driver" if COMPILE_TEST
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depends on COMMON_CLK
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@ -56,6 +56,7 @@ obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
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obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o
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obj-$(CONFIG_OWL_TIMER) += owl-timer.o
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obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o
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obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o
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obj-$(CONFIG_ARC_TIMERS) += arc_timer.o
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obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
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@ -17,9 +17,14 @@
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#include <linux/of_irq.h>
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#include <linux/sched_clock.h>
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#define TPM_PARAM 0x4
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#define TPM_PARAM_WIDTH_SHIFT 16
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#define TPM_PARAM_WIDTH_MASK (0xff << 16)
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#define TPM_SC 0x10
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#define TPM_SC_CMOD_INC_PER_CNT (0x1 << 3)
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#define TPM_SC_CMOD_DIV_DEFAULT 0x3
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#define TPM_SC_CMOD_DIV_MAX 0x7
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#define TPM_SC_TOF_MASK (0x1 << 7)
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#define TPM_CNT 0x14
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#define TPM_MOD 0x18
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#define TPM_STATUS 0x1c
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@ -29,8 +34,11 @@
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#define TPM_C0SC_MODE_SHIFT 2
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#define TPM_C0SC_MODE_MASK 0x3c
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#define TPM_C0SC_MODE_SW_COMPARE 0x4
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#define TPM_C0SC_CHF_MASK (0x1 << 7)
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#define TPM_C0V 0x24
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static int counter_width;
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static int rating;
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static void __iomem *timer_base;
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static struct clock_event_device clockevent_tpm;
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@ -83,10 +91,11 @@ static int __init tpm_clocksource_init(unsigned long rate)
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tpm_delay_timer.freq = rate;
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register_current_timer_delay(&tpm_delay_timer);
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sched_clock_register(tpm_read_sched_clock, 32, rate);
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sched_clock_register(tpm_read_sched_clock, counter_width, rate);
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return clocksource_mmio_init(timer_base + TPM_CNT, "imx-tpm",
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rate, 200, 32, clocksource_mmio_readl_up);
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rate, rating, counter_width,
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clocksource_mmio_readl_up);
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}
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static int tpm_set_next_event(unsigned long delta,
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@ -139,7 +148,6 @@ static struct clock_event_device clockevent_tpm = {
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.set_state_oneshot = tpm_set_state_oneshot,
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.set_next_event = tpm_set_next_event,
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.set_state_shutdown = tpm_set_state_shutdown,
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.rating = 200,
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};
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static int __init tpm_clockevent_init(unsigned long rate, int irq)
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@ -149,10 +157,11 @@ static int __init tpm_clockevent_init(unsigned long rate, int irq)
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ret = request_irq(irq, tpm_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
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"i.MX7ULP TPM Timer", &clockevent_tpm);
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clockevent_tpm.rating = rating;
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clockevent_tpm.cpumask = cpumask_of(0);
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clockevent_tpm.irq = irq;
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clockevents_config_and_register(&clockevent_tpm,
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rate, 300, 0xfffffffe);
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clockevents_config_and_register(&clockevent_tpm, rate, 300,
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GENMASK(counter_width - 1, 1));
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return ret;
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}
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@ -179,7 +188,7 @@ static int __init tpm_timer_init(struct device_node *np)
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ipg = of_clk_get_by_name(np, "ipg");
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per = of_clk_get_by_name(np, "per");
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if (IS_ERR(ipg) || IS_ERR(per)) {
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pr_err("tpm: failed to get igp or per clk\n");
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pr_err("tpm: failed to get ipg or per clk\n");
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ret = -ENODEV;
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goto err_clk_get;
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}
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@ -197,6 +206,11 @@ static int __init tpm_timer_init(struct device_node *np)
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goto err_per_clk_enable;
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}
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counter_width = (readl(timer_base + TPM_PARAM) & TPM_PARAM_WIDTH_MASK)
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>> TPM_PARAM_WIDTH_SHIFT;
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/* use rating 200 for 32-bit counter and 150 for 16-bit counter */
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rating = counter_width == 0x20 ? 200 : 150;
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/*
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* Initialize tpm module to a known state
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* 1) Counter disabled
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@ -205,16 +219,25 @@ static int __init tpm_timer_init(struct device_node *np)
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* 4) Channel0 disabled
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* 5) DMA transfers disabled
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*/
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/* make sure counter is disabled */
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writel(0, timer_base + TPM_SC);
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/* TOF is W1C */
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writel(TPM_SC_TOF_MASK, timer_base + TPM_SC);
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writel(0, timer_base + TPM_CNT);
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writel(0, timer_base + TPM_C0SC);
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/* CHF is W1C */
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writel(TPM_C0SC_CHF_MASK, timer_base + TPM_C0SC);
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/* increase per cnt, div 8 by default */
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writel(TPM_SC_CMOD_INC_PER_CNT | TPM_SC_CMOD_DIV_DEFAULT,
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/*
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* increase per cnt,
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* div 8 for 32-bit counter and div 128 for 16-bit counter
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*/
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writel(TPM_SC_CMOD_INC_PER_CNT |
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(counter_width == 0x20 ?
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TPM_SC_CMOD_DIV_DEFAULT : TPM_SC_CMOD_DIV_MAX),
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timer_base + TPM_SC);
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/* set MOD register to maximum for free running mode */
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writel(0xffffffff, timer_base + TPM_MOD);
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writel(GENMASK(counter_width - 1, 0), timer_base + TPM_MOD);
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rate = clk_get_rate(per) >> 3;
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ret = tpm_clocksource_init(rate);
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@ -0,0 +1,215 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2014-2018 Nuvoton Technologies tomer.maimon@nuvoton.com
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* All rights reserved.
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*
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* Copyright 2017 Google, Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/clockchips.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include "timer-of.h"
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/* Timers registers */
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#define NPCM7XX_REG_TCSR0 0x0 /* Timer 0 Control and Status Register */
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#define NPCM7XX_REG_TICR0 0x8 /* Timer 0 Initial Count Register */
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#define NPCM7XX_REG_TCSR1 0x4 /* Timer 1 Control and Status Register */
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#define NPCM7XX_REG_TICR1 0xc /* Timer 1 Initial Count Register */
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#define NPCM7XX_REG_TDR1 0x14 /* Timer 1 Data Register */
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#define NPCM7XX_REG_TISR 0x18 /* Timer Interrupt Status Register */
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/* Timers control */
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#define NPCM7XX_Tx_RESETINT 0x1f
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#define NPCM7XX_Tx_PERIOD BIT(27)
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#define NPCM7XX_Tx_INTEN BIT(29)
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#define NPCM7XX_Tx_COUNTEN BIT(30)
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#define NPCM7XX_Tx_ONESHOT 0x0
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#define NPCM7XX_Tx_OPER GENMASK(3, 27)
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#define NPCM7XX_Tx_MIN_PRESCALE 0x1
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#define NPCM7XX_Tx_TDR_MASK_BITS 24
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#define NPCM7XX_Tx_MAX_CNT 0xFFFFFF
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#define NPCM7XX_T0_CLR_INT 0x1
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#define NPCM7XX_Tx_CLR_CSR 0x0
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/* Timers operating mode */
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#define NPCM7XX_START_PERIODIC_Tx (NPCM7XX_Tx_PERIOD | NPCM7XX_Tx_COUNTEN | \
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NPCM7XX_Tx_INTEN | \
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NPCM7XX_Tx_MIN_PRESCALE)
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#define NPCM7XX_START_ONESHOT_Tx (NPCM7XX_Tx_ONESHOT | NPCM7XX_Tx_COUNTEN | \
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NPCM7XX_Tx_INTEN | \
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NPCM7XX_Tx_MIN_PRESCALE)
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#define NPCM7XX_START_Tx (NPCM7XX_Tx_COUNTEN | NPCM7XX_Tx_PERIOD | \
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NPCM7XX_Tx_MIN_PRESCALE)
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#define NPCM7XX_DEFAULT_CSR (NPCM7XX_Tx_CLR_CSR | NPCM7XX_Tx_MIN_PRESCALE)
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static int npcm7xx_timer_resume(struct clock_event_device *evt)
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{
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struct timer_of *to = to_timer_of(evt);
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u32 val;
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val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
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val |= NPCM7XX_Tx_COUNTEN;
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writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
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return 0;
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}
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static int npcm7xx_timer_shutdown(struct clock_event_device *evt)
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{
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struct timer_of *to = to_timer_of(evt);
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u32 val;
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val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
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val &= ~NPCM7XX_Tx_COUNTEN;
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writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
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return 0;
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}
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static int npcm7xx_timer_oneshot(struct clock_event_device *evt)
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{
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struct timer_of *to = to_timer_of(evt);
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u32 val;
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val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
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val &= ~NPCM7XX_Tx_OPER;
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val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
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val |= NPCM7XX_START_ONESHOT_Tx;
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writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
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return 0;
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}
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static int npcm7xx_timer_periodic(struct clock_event_device *evt)
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{
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struct timer_of *to = to_timer_of(evt);
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u32 val;
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val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
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val &= ~NPCM7XX_Tx_OPER;
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writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
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val |= NPCM7XX_START_PERIODIC_Tx;
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writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
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return 0;
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}
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static int npcm7xx_clockevent_set_next_event(unsigned long evt,
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struct clock_event_device *clk)
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{
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struct timer_of *to = to_timer_of(clk);
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u32 val;
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writel(evt, timer_of_base(to) + NPCM7XX_REG_TICR0);
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val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
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val |= NPCM7XX_START_Tx;
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writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
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return 0;
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}
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static irqreturn_t npcm7xx_timer0_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = (struct clock_event_device *)dev_id;
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struct timer_of *to = to_timer_of(evt);
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writel(NPCM7XX_T0_CLR_INT, timer_of_base(to) + NPCM7XX_REG_TISR);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct timer_of npcm7xx_to = {
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.flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
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.clkevt = {
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.name = "npcm7xx-timer0",
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.features = CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_ONESHOT,
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.set_next_event = npcm7xx_clockevent_set_next_event,
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.set_state_shutdown = npcm7xx_timer_shutdown,
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.set_state_periodic = npcm7xx_timer_periodic,
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.set_state_oneshot = npcm7xx_timer_oneshot,
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.tick_resume = npcm7xx_timer_resume,
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.rating = 300,
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},
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.of_irq = {
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.handler = npcm7xx_timer0_interrupt,
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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},
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};
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static void __init npcm7xx_clockevents_init(void)
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{
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writel(NPCM7XX_DEFAULT_CSR,
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timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR0);
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writel(NPCM7XX_Tx_RESETINT,
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timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TISR);
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npcm7xx_to.clkevt.cpumask = cpumask_of(0);
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clockevents_config_and_register(&npcm7xx_to.clkevt,
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timer_of_rate(&npcm7xx_to),
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0x1, NPCM7XX_Tx_MAX_CNT);
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}
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static void __init npcm7xx_clocksource_init(void)
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{
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u32 val;
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writel(NPCM7XX_DEFAULT_CSR,
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timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1);
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writel(NPCM7XX_Tx_MAX_CNT,
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timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TICR1);
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val = readl(timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1);
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val |= NPCM7XX_START_Tx;
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writel(val, timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1);
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clocksource_mmio_init(timer_of_base(&npcm7xx_to) +
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NPCM7XX_REG_TDR1,
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"npcm7xx-timer1", timer_of_rate(&npcm7xx_to),
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200, (unsigned int)NPCM7XX_Tx_TDR_MASK_BITS,
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clocksource_mmio_readl_down);
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}
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static int __init npcm7xx_timer_init(struct device_node *np)
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{
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int ret;
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ret = timer_of_init(np, &npcm7xx_to);
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if (ret)
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return ret;
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/* Clock input is divided by PRESCALE + 1 before it is fed */
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/* to the counter */
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npcm7xx_to.of_clk.rate = npcm7xx_to.of_clk.rate /
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(NPCM7XX_Tx_MIN_PRESCALE + 1);
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npcm7xx_clocksource_init();
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npcm7xx_clockevents_init();
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pr_info("Enabling NPCM7xx clocksource timer base: %px, IRQ: %d ",
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timer_of_base(&npcm7xx_to), timer_of_irq(&npcm7xx_to));
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return 0;
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}
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TIMER_OF_DECLARE(npcm7xx, "nuvoton,npcm750-timer", npcm7xx_timer_init);
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