Samsung mach/soc changes for v5.3
Only cleanups and minor fixes. -----BEGIN PGP SIGNATURE----- iQJDBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAl0SdncQHGtyemtAa2Vy bmVsLm9yZwAKCRDBN2bmhouD1730D/d1FaVbBxX0usjsWufS9IkQe4XvRk8KiAOk gjjkp5rePkwXkezWjsS4vSrvN0dP39J7U0HFq9J4yqUNNL4UoKGZIU4pUZM+YNMS i3IXWK+p963smP9pwFWbHNP8BnMucS2PrWGt3gI2fpJ2u/+Nidc7Hg4q80GqHsi5 XXGO5xHEWXsPsDaypaYerEMZm79QRlvSbogGDYWhhh3VAvFZdV19rOo7YUwN6aA9 S9PQb2OjBspGQjtfz3MXBpkpjbgcM9xS/ocnRaV2/EkrY8xndHLz3Xrrdaz1BeIi Rbp8bkUYC6ibb1xwC8+61JUNz2tzuvyuZUl55ak8dat5Xn186ww6f8E+em6gHhgf kkaU+KTuiOcG4oigqzZljiw9GNm3o7Sp4PaZzjcxougd0i0/vvtiZR8jkRqnB2BG CmhN7mIIecj9KwRYWy7S/zYAw3AIXLx9uWSO9Qvp1ASE3Bvmcbfvbtl+rQ5a00Ct A23jl2irUEj9ya2IOy9Vo7xoiqfV2Z4sJRt9oPo2l3qCCv7z1dGEV+0N6ySX6HHQ f5wsafCeGuOb1GhX+jwt6JosgQzI3kTZaoNR8CfONyaj+YY8Q5wfNNLtStlBrguv c9/xx1YCqp5qHxYaaLS9ozLT42wcT/Cv6ksapRMip9f61Cu1GwsHlFnvlGLdwUBC 85nG5cqW =b9yN -----END PGP SIGNATURE----- Merge tag 'samsung-soc-5.3' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/soc Samsung mach/soc changes for v5.3 Only cleanups and minor fixes. * tag 'samsung-soc-5.3' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: exynos: Cleanup cppcheck shifting warning ARM: exynos: Only build MCPM support if used ARM: exynos: Make ARCH_EXYNOS3 a default option Signed-off-by: Olof Johansson <olof@lixom.net>
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commit
da4d0b2891
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@ -49,6 +49,7 @@ config S5P_DEV_MFC
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config ARCH_EXYNOS3
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config ARCH_EXYNOS3
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bool "SAMSUNG EXYNOS3"
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bool "SAMSUNG EXYNOS3"
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default y
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select ARM_CPU_SUSPEND if PM
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select ARM_CPU_SUSPEND if PM
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help
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help
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Samsung EXYNOS3 (Cortex-A7) SoC based systems
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Samsung EXYNOS3 (Cortex-A7) SoC based systems
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@ -106,7 +107,7 @@ config SOC_EXYNOS5420
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bool "SAMSUNG EXYNOS5420"
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bool "SAMSUNG EXYNOS5420"
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default y
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default y
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depends on ARCH_EXYNOS5
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depends on ARCH_EXYNOS5
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select MCPM if SMP
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select EXYNOS_MCPM if SMP
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select ARM_CCI400_PORT_CTRL
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select ARM_CCI400_PORT_CTRL
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select ARM_CPU_SUSPEND
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select ARM_CPU_SUSPEND
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@ -115,6 +116,10 @@ config SOC_EXYNOS5800
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default y
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default y
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depends on SOC_EXYNOS5420
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depends on SOC_EXYNOS5420
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config EXYNOS_MCPM
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bool
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select MCPM
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config EXYNOS_CPU_SUSPEND
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config EXYNOS_CPU_SUSPEND
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bool
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bool
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select ARM_CPU_SUSPEND
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select ARM_CPU_SUSPEND
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@ -14,5 +14,5 @@ obj-$(CONFIG_PM_SLEEP) += suspend.o
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obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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obj-$(CONFIG_MCPM) += mcpm-exynos.o
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obj-$(CONFIG_EXYNOS_MCPM) += mcpm-exynos.o
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CFLAGS_mcpm-exynos.o += -march=armv7-a
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CFLAGS_mcpm-exynos.o += -march=armv7-a
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@ -268,7 +268,7 @@ static int exynos5420_cpu_suspend(unsigned long arg)
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unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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if (IS_ENABLED(CONFIG_MCPM)) {
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if (IS_ENABLED(CONFIG_EXYNOS_MCPM)) {
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mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
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mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
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mcpm_cpu_suspend();
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mcpm_cpu_suspend();
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}
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}
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@ -285,7 +285,7 @@ static void exynos_pm_set_wakeup_mask(void)
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* Set wake-up mask registers
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* Set wake-up mask registers
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* EXYNOS_EINT_WAKEUP_MASK is set by pinctrl driver in late suspend.
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* EXYNOS_EINT_WAKEUP_MASK is set by pinctrl driver in late suspend.
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*/
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*/
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pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
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pmu_raw_writel(exynos_irqwake_intmask & ~BIT(31), S5P_WAKEUP_MASK);
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}
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}
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static void exynos_pm_enter_sleep_mode(void)
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static void exynos_pm_enter_sleep_mode(void)
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@ -351,7 +351,7 @@ static void exynos5420_pm_prepare(void)
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exynos_pm_enter_sleep_mode();
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exynos_pm_enter_sleep_mode();
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/* ensure at least INFORM0 has the resume address */
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/* ensure at least INFORM0 has the resume address */
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if (IS_ENABLED(CONFIG_MCPM))
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if (IS_ENABLED(CONFIG_EXYNOS_MCPM))
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pmu_raw_writel(__pa_symbol(mcpm_entry_point), S5P_INFORM0);
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pmu_raw_writel(__pa_symbol(mcpm_entry_point), S5P_INFORM0);
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tmp = pmu_raw_readl(EXYNOS_L2_OPTION(0));
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tmp = pmu_raw_readl(EXYNOS_L2_OPTION(0));
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@ -455,7 +455,7 @@ static void exynos5420_prepare_pm_resume(void)
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mpidr = read_cpuid_mpidr();
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mpidr = read_cpuid_mpidr();
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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if (IS_ENABLED(CONFIG_MCPM))
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if (IS_ENABLED(CONFIG_EXYNOS_MCPM))
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WARN_ON(mcpm_cpu_powered_up());
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WARN_ON(mcpm_cpu_powered_up());
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if (IS_ENABLED(CONFIG_HW_PERF_EVENTS) && cluster != 0) {
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if (IS_ENABLED(CONFIG_HW_PERF_EVENTS) && cluster != 0) {
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