pwm: Changes for v4.17-rc1
This set of changes adds support for more generations of the RCar controller as well as runtime PM support. The JZ4740 driver gains support for device tree and can now be used on all Ingenic SoCs. Rounding things off is a random assortment of fixes and cleanups all across the board. -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlrPJeAZHHRoaWVycnku cmVkaW5nQGdtYWlsLmNvbQAKCRDdI6zXfz6zoUQvEACaAkXPs3rvvHVF7pDo7SMV 3WMJu1oOiZ7Gy0VAooRyhwI/rNBeF4PYuHuxa2+NeuWX8MBN41dRWAp8Am4kMnOE Lxp259qQTNGdGQTnSXP/sbYTKzAqF/3G0XtkhGejS3AzYSnhk6sIGcCevS4MD8bV I/jSigPO4ByizyEJsnAkZPUw5js2CsE2xSnGKRsITZBK7yDi/cwB2cOLm0+psCKu qYTlOHTc3myRKYESw5rmzB+cRyLGMkaq9SQzLZ8E2PP7zIY1QbrmzufQ1ovbpffl 065dS8+m1ecRMXUfFCLnHZPk/S5W6xZMskVJ0GIKC3xBPefbpCkkcA9A/gXkwH4y FJ4lCROnB8gE3ITGkqzmZNBt3PKySIubEv1mCzdHVx3j4IEmF/M1Xc4wxz9qD+tD ay+h1Vv1RbQlYlMqcOkxBpZd6sUnDIlIvIJ35IYUvD80Ap24DIU05NR1xsq6DMaD c0N13an4gyK1t2O0YRcdmhHhIgwwaGhka5+8+r2hCqSVf/uzgyn26vzyqttrHuVc CNYeMObuotr72LVHzXHkr4I/h+c7KE1B8RYKLZvUQuIdOvSb7Z9n32n1dBRILDH8 ppb+Y4azLDvAF4SAt5lZhYsMmB8vuCp4TA5LKwBEsylwTwOL9ghL7luYAOF4UroH qigluQk3Sf5GF1jrp9hTew== =JiRM -----END PGP SIGNATURE----- Merge tag 'pwm/for-4.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm Pull pwm updates from Thierry Reding: "This set of changes adds support for more generations of the RCar controller as well as runtime PM support. The JZ4740 driver gains support for device tree and can now be used on all Ingenic SoCs. Rounding things off is a random assortment of fixes and cleanups all across the board" * tag 'pwm/for-4.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: (29 commits) pwm: rcar: Add suspend/resume support pwm: rcar: Use PM Runtime to control module clock dt-bindings: pwm: rcar: Add bindings for R-Car M3N support pwm: rcar: Fix a condition to prevent mismatch value setting to duty pwm: sysfs: Use put_device() instead of kfree() dt-bindings: pwm: sunxi: Add new compatible strings pwm: sun4i: Simplify controller mapping pwm: sun4i: Drop unused .has_rdy member pwm: sun4i: Properly check current state pwm: Remove depends on AVR32 pwm: stm32: LPTimer: Use 3 cells ->of_xlate() dt-bindings: pwm-stm32-lp: Add #pwm-cells pwm: stm32: Protect common prescaler for all channels pwm: stm32: Remove unused struct device pwm: mediatek: Improve precision in rate calculation pwm: mediatek: Remove redundant MODULE_ALIAS entries pwm: mediatek: Fix up PWM4 and PWM5 malfunction on MT7623 pwm: jz4740: Enable for all Ingenic SoCs pwm: jz4740: Add support for devicetree pwm: jz4740: Implement ->set_polarity() ...
This commit is contained in:
Linus Torvalds
commit
daf3ef6e96
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@ -0,0 +1,25 @@
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Ingenic JZ47xx PWM Controller
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=============================
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Required properties:
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- compatible: One of:
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* "ingenic,jz4740-pwm"
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* "ingenic,jz4770-pwm"
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* "ingenic,jz4780-pwm"
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- #pwm-cells: Should be 3. See pwm.txt in this directory for a description
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of the cells format.
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- clocks : phandle to the external clock.
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- clock-names : Should be "ext".
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Example:
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pwm: pwm@10002000 {
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compatible = "ingenic,jz4740-pwm";
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reg = <0x10002000 0x1000>;
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#pwm-cells = <3>;
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clocks = <&ext>;
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clock-names = "ext";
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};
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@ -7,6 +7,8 @@ See ../mfd/stm32-lptimer.txt for details about the parent node.
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Required parameters:
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- compatible: Must be "st,stm32-pwm-lp".
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- #pwm-cells: Should be set to 3. This PWM chip uses the default 3 cells
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bindings defined in pwm.txt.
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Optional properties:
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- pinctrl-names: Set to "default".
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@ -18,6 +20,7 @@ Example:
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...
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pwm {
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compatible = "st,stm32-pwm-lp";
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#pwm-cells = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&lppwm1_pins>;
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};
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@ -7,6 +7,8 @@ Required properties:
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- "allwinner,sun5i-a13-pwm"
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- "allwinner,sun7i-a20-pwm"
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- "allwinner,sun8i-h3-pwm"
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- "allwinner,sun50i-a64-pwm", "allwinner,sun5i-a13-pwm"
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- "allwinner,sun50i-h5-pwm", "allwinner,sun5i-a13-pwm"
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- reg: physical base address and length of the controller's registers
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- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
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the cells format.
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@ -2,6 +2,8 @@
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Required Properties:
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- compatible: should be "renesas,pwm-rcar" and one of the following.
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- "renesas,pwm-r8a7743": for RZ/G1M
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- "renesas,pwm-r8a7745": for RZ/G1E
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- "renesas,pwm-r8a7778": for R-Car M1A
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- "renesas,pwm-r8a7779": for R-Car H1
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- "renesas,pwm-r8a7790": for R-Car H2
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@ -9,6 +11,7 @@ Required Properties:
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- "renesas,pwm-r8a7794": for R-Car E2
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- "renesas,pwm-r8a7795": for R-Car H3
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- "renesas,pwm-r8a7796": for R-Car M3-W
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- "renesas,pwm-r8a77965": for R-Car M3-N
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- "renesas,pwm-r8a77995": for R-Car D3
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- reg: base address and length of the registers block for the PWM.
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- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
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@ -17,13 +20,15 @@ Required Properties:
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- pinctrl-0: phandle, referring to a default pin configuration node.
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- pinctrl-names: Set to "default".
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Example: R8A7790 (R-Car H2) PWM Timer node
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Example: R8A7743 (RZ/G1M) PWM Timer node
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pwm0: pwm@e6e30000 {
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compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
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compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
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reg = <0 0xe6e30000 0 0x8>;
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clocks = <&cpg CPG_MOD 523>;
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power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
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resets = <&cpg 523>;
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#pwm-cells = <2>;
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clocks = <&mstp5_clks R8A7790_CLK_PWM>;
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pinctrl-0 = <&pwm0_pins>;
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pinctrl-names = "default";
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};
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@ -3,10 +3,12 @@
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Required Properties:
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- compatible: should be one of the following.
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- "renesas,tpu-r8a73a4": for R8A77A4 (R-Mobile APE6) compatible PWM controller.
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- "renesas,tpu-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible PWM controller.
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- "renesas,tpu-r8a7740": for R8A7740 (R-Mobile A1) compatible PWM controller.
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- "renesas,tpu-r8a7743": for R8A7743 (RZ/G1M) compatible PWM controller.
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- "renesas,tpu-r8a7745": for R8A7745 (RZ/G1E) compatible PWM controller.
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- "renesas,tpu-r8a7790": for R8A7790 (R-Car H2) compatible PWM controller.
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- "renesas,tpu": for generic R-Car TPU PWM controller.
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- "renesas,tpu": for generic R-Car and RZ/G1 TPU PWM controller.
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- reg: Base address and length of each memory resource used by the PWM
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controller hardware module.
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@ -18,10 +20,10 @@ Required Properties:
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Please refer to pwm.txt in this directory for details of the common PWM bindings
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used by client devices.
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Example: R8A7740 (R-Car A1) TPU controller node
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Example: R8A7740 (R-Mobile A1) TPU controller node
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tpu: pwm@e6600000 {
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compatible = "renesas,tpu-r8a7740", "renesas,tpu";
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reg = <0xe6600000 0x100>;
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reg = <0xe6600000 0x148>;
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#pwm-cells = <3>;
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};
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@ -200,10 +200,10 @@ config PWM_IMX
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will be called pwm-imx.
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config PWM_JZ4740
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tristate "Ingenic JZ4740 PWM support"
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depends on MACH_JZ4740
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tristate "Ingenic JZ47xx PWM support"
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depends on MACH_INGENIC
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help
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Generic PWM framework driver for Ingenic JZ4740 based
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Generic PWM framework driver for Ingenic JZ47xx based
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machines.
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To compile this driver as a module, choose M here: the module
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@ -401,7 +401,6 @@ static int atmel_tcb_pwm_probe(struct platform_device *pdev)
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tcbpwm = devm_kzalloc(&pdev->dev, sizeof(*tcbpwm), GFP_KERNEL);
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if (tcbpwm == NULL) {
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err = -ENOMEM;
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dev_err(&pdev->dev, "failed to allocate memory\n");
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goto err_free_tc;
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}
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@ -35,6 +35,7 @@
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#define MX3_PWMSAR 0x0C /* PWM Sample Register */
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#define MX3_PWMPR 0x10 /* PWM Period Register */
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#define MX3_PWMCR_PRESCALER(x) ((((x) - 1) & 0xFFF) << 4)
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#define MX3_PWMCR_STOPEN (1 << 25)
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#define MX3_PWMCR_DOZEEN (1 << 24)
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#define MX3_PWMCR_WAITEN (1 << 23)
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#define MX3_PWMCR_DBGEN (1 << 22)
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@ -210,7 +211,7 @@ static int imx_pwm_apply_v2(struct pwm_chip *chip, struct pwm_device *pwm,
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writel(period_cycles, imx->mmio_base + MX3_PWMPR);
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cr = MX3_PWMCR_PRESCALER(prescale) |
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MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
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MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
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MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH |
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MX3_PWMCR_EN;
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@ -18,6 +18,7 @@
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#include <linux/gpio.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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@ -71,9 +72,15 @@ static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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uint32_t ctrl = jz4740_timer_get_ctrl(pwm->hwpwm);
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/* Disable PWM output.
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* In TCU2 mode (channel 1/2 on JZ4750+), this must be done before the
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* counter is stopped, while in TCU1 mode the order does not matter.
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*/
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ctrl &= ~JZ_TIMER_CTRL_PWM_ENABLE;
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jz4740_timer_disable(pwm->hwpwm);
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jz4740_timer_set_ctrl(pwm->hwpwm, ctrl);
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/* Stop counter */
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jz4740_timer_disable(pwm->hwpwm);
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}
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static int jz4740_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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@ -124,10 +131,29 @@ static int jz4740_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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return 0;
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}
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static int jz4740_pwm_set_polarity(struct pwm_chip *chip,
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struct pwm_device *pwm, enum pwm_polarity polarity)
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{
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uint32_t ctrl = jz4740_timer_get_ctrl(pwm->pwm);
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switch (polarity) {
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case PWM_POLARITY_NORMAL:
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ctrl &= ~JZ_TIMER_CTRL_PWM_ACTIVE_LOW;
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break;
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case PWM_POLARITY_INVERSED:
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ctrl |= JZ_TIMER_CTRL_PWM_ACTIVE_LOW;
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break;
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}
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jz4740_timer_set_ctrl(pwm->hwpwm, ctrl);
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return 0;
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}
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static const struct pwm_ops jz4740_pwm_ops = {
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.request = jz4740_pwm_request,
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.free = jz4740_pwm_free,
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.config = jz4740_pwm_config,
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.set_polarity = jz4740_pwm_set_polarity,
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.enable = jz4740_pwm_enable,
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.disable = jz4740_pwm_disable,
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.owner = THIS_MODULE,
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@ -149,6 +175,8 @@ static int jz4740_pwm_probe(struct platform_device *pdev)
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jz4740->chip.ops = &jz4740_pwm_ops;
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jz4740->chip.npwm = NUM_PWM;
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jz4740->chip.base = -1;
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jz4740->chip.of_xlate = of_pwm_xlate_with_flags;
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jz4740->chip.of_pwm_n_cells = 3;
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platform_set_drvdata(pdev, jz4740);
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@ -162,9 +190,20 @@ static int jz4740_pwm_remove(struct platform_device *pdev)
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return pwmchip_remove(&jz4740->chip);
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}
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#ifdef CONFIG_OF
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static const struct of_device_id jz4740_pwm_dt_ids[] = {
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{ .compatible = "ingenic,jz4740-pwm", },
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{ .compatible = "ingenic,jz4770-pwm", },
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{ .compatible = "ingenic,jz4780-pwm", },
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{},
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};
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MODULE_DEVICE_TABLE(of, jz4740_pwm_dt_ids);
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#endif
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static struct platform_driver jz4740_pwm_driver = {
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.driver = {
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.name = "jz4740-pwm",
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.of_match_table = of_match_ptr(jz4740_pwm_dt_ids),
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},
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.probe = jz4740_pwm_probe,
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.remove = jz4740_pwm_remove,
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@ -29,7 +29,9 @@
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#define PWMGDUR 0x0c
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#define PWMWAVENUM 0x28
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#define PWMDWIDTH 0x2c
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#define PWM45DWIDTH_FIXUP 0x30
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#define PWMTHRES 0x30
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#define PWM45THRES_FIXUP 0x34
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#define PWM_CLK_DIV_MAX 7
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@ -54,6 +56,7 @@ static const char * const mtk_pwm_clk_name[MTK_CLK_MAX] = {
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struct mtk_pwm_platform_data {
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unsigned int num_pwms;
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bool pwm45_fixup;
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};
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/**
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@ -66,6 +69,7 @@ struct mtk_pwm_chip {
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struct pwm_chip chip;
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void __iomem *regs;
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struct clk *clks[MTK_CLK_MAX];
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const struct mtk_pwm_platform_data *soc;
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};
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static const unsigned int mtk_pwm_reg_offset[] = {
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|
@ -131,18 +135,25 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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{
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struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
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struct clk *clk = pc->clks[MTK_CLK_PWM1 + pwm->hwpwm];
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u32 resolution, clkdiv = 0;
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u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
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reg_thres = PWMTHRES;
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u64 resolution;
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int ret;
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ret = mtk_pwm_clk_enable(chip, pwm);
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if (ret < 0)
|
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return ret;
|
||||
|
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resolution = NSEC_PER_SEC / clk_get_rate(clk);
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/* Using resolution in picosecond gets accuracy higher */
|
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resolution = (u64)NSEC_PER_SEC * 1000;
|
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do_div(resolution, clk_get_rate(clk));
|
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|
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while (period_ns / resolution > 8191) {
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cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
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while (cnt_period > 8191) {
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resolution *= 2;
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clkdiv++;
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cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
|
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resolution);
|
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}
|
||||
|
||||
if (clkdiv > PWM_CLK_DIV_MAX) {
|
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|
|
@ -151,9 +162,19 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
|
||||
/*
|
||||
* PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
|
||||
* from the other PWMs on MT7623.
|
||||
*/
|
||||
reg_width = PWM45DWIDTH_FIXUP;
|
||||
reg_thres = PWM45THRES_FIXUP;
|
||||
}
|
||||
|
||||
cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
|
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mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
|
||||
mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
|
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mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);
|
||||
mtk_pwm_writel(pc, pwm->hwpwm, reg_width, cnt_period);
|
||||
mtk_pwm_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
|
||||
|
||||
mtk_pwm_clk_disable(chip, pwm);
|
||||
|
||||
|
|
@ -211,6 +232,7 @@ static int mtk_pwm_probe(struct platform_device *pdev)
|
|||
data = of_device_get_match_data(&pdev->dev);
|
||||
if (data == NULL)
|
||||
return -EINVAL;
|
||||
pc->soc = data;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
pc->regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
|
|
@ -251,14 +273,17 @@ static int mtk_pwm_remove(struct platform_device *pdev)
|
|||
|
||||
static const struct mtk_pwm_platform_data mt2712_pwm_data = {
|
||||
.num_pwms = 8,
|
||||
.pwm45_fixup = false,
|
||||
};
|
||||
|
||||
static const struct mtk_pwm_platform_data mt7622_pwm_data = {
|
||||
.num_pwms = 6,
|
||||
.pwm45_fixup = false,
|
||||
};
|
||||
|
||||
static const struct mtk_pwm_platform_data mt7623_pwm_data = {
|
||||
.num_pwms = 5,
|
||||
.pwm45_fixup = true,
|
||||
};
|
||||
|
||||
static const struct of_device_id mtk_pwm_of_match[] = {
|
||||
|
|
@ -280,5 +305,4 @@ static struct platform_driver mtk_pwm_driver = {
|
|||
module_platform_driver(mtk_pwm_driver);
|
||||
|
||||
MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
|
||||
MODULE_ALIAS("platform:mtk-pwm");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
|
|||
|
|
@ -107,10 +107,8 @@ static int pwm_probe(struct platform_device *pdev)
|
|||
int ret;
|
||||
|
||||
puv3 = devm_kzalloc(&pdev->dev, sizeof(*puv3), GFP_KERNEL);
|
||||
if (puv3 == NULL) {
|
||||
dev_err(&pdev->dev, "failed to allocate memory\n");
|
||||
if (!puv3)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
puv3->clk = devm_clk_get(&pdev->dev, "OST_CLK");
|
||||
if (IS_ERR(puv3->clk))
|
||||
|
|
|
|||
|
|
@ -134,16 +134,12 @@ static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, int duty_ns,
|
|||
|
||||
static int rcar_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
|
||||
{
|
||||
struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
|
||||
|
||||
return clk_prepare_enable(rp->clk);
|
||||
return pm_runtime_get_sync(chip->dev);
|
||||
}
|
||||
|
||||
static void rcar_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
|
||||
{
|
||||
struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
|
||||
|
||||
clk_disable_unprepare(rp->clk);
|
||||
pm_runtime_put(chip->dev);
|
||||
}
|
||||
|
||||
static int rcar_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
|
||||
|
|
@ -156,8 +152,12 @@ static int rcar_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
|
|||
if (div < 0)
|
||||
return div;
|
||||
|
||||
/* Let the core driver set pwm->period if disabled and duty_ns == 0 */
|
||||
if (!pwm_is_enabled(pwm) && !duty_ns)
|
||||
/*
|
||||
* Let the core driver set pwm->period if disabled and duty_ns == 0.
|
||||
* But, this driver should prevent to set the new duty_ns if current
|
||||
* duty_cycle is not set
|
||||
*/
|
||||
if (!pwm_is_enabled(pwm) && !duty_ns && !pwm->state.duty_cycle)
|
||||
return 0;
|
||||
|
||||
rcar_pwm_update(rp, RCAR_PWMCR_SYNC, RCAR_PWMCR_SYNC, RCAR_PWMCR);
|
||||
|
|
@ -258,11 +258,53 @@ static const struct of_device_id rcar_pwm_of_table[] = {
|
|||
};
|
||||
MODULE_DEVICE_TABLE(of, rcar_pwm_of_table);
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct pwm_device *rcar_pwm_dev_to_pwm_dev(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct rcar_pwm_chip *rcar_pwm = platform_get_drvdata(pdev);
|
||||
struct pwm_chip *chip = &rcar_pwm->chip;
|
||||
|
||||
return &chip->pwms[0];
|
||||
}
|
||||
|
||||
static int rcar_pwm_suspend(struct device *dev)
|
||||
{
|
||||
struct pwm_device *pwm = rcar_pwm_dev_to_pwm_dev(dev);
|
||||
|
||||
if (!test_bit(PWMF_REQUESTED, &pwm->flags))
|
||||
return 0;
|
||||
|
||||
pm_runtime_put(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rcar_pwm_resume(struct device *dev)
|
||||
{
|
||||
struct pwm_device *pwm = rcar_pwm_dev_to_pwm_dev(dev);
|
||||
|
||||
if (!test_bit(PWMF_REQUESTED, &pwm->flags))
|
||||
return 0;
|
||||
|
||||
pm_runtime_get_sync(dev);
|
||||
|
||||
rcar_pwm_config(pwm->chip, pwm, pwm->state.duty_cycle,
|
||||
pwm->state.period);
|
||||
if (pwm_is_enabled(pwm))
|
||||
rcar_pwm_enable(pwm->chip, pwm);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_PM_SLEEP */
|
||||
static SIMPLE_DEV_PM_OPS(rcar_pwm_pm_ops, rcar_pwm_suspend, rcar_pwm_resume);
|
||||
|
||||
static struct platform_driver rcar_pwm_driver = {
|
||||
.probe = rcar_pwm_probe,
|
||||
.remove = rcar_pwm_remove,
|
||||
.driver = {
|
||||
.name = "pwm-rcar",
|
||||
.pm = &rcar_pwm_pm_ops,
|
||||
.of_match_table = of_match_ptr(rcar_pwm_of_table),
|
||||
}
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* STM32 Low-Power Timer PWM driver
|
||||
*
|
||||
|
|
@ -5,8 +6,6 @@
|
|||
*
|
||||
* Author: Gerald Baeza <gerald.baeza@st.com>
|
||||
*
|
||||
* License terms: GNU General Public License (GPL), version 2
|
||||
*
|
||||
* Inspired by Gerald Baeza's pwm-stm32 driver
|
||||
*/
|
||||
|
||||
|
|
@ -203,6 +202,8 @@ static int stm32_pwm_lp_probe(struct platform_device *pdev)
|
|||
priv->chip.dev = &pdev->dev;
|
||||
priv->chip.ops = &stm32_pwm_lp_ops;
|
||||
priv->chip.npwm = 1;
|
||||
priv->chip.of_xlate = of_pwm_xlate_with_flags;
|
||||
priv->chip.of_pwm_n_cells = 3;
|
||||
|
||||
ret = pwmchip_add(&priv->chip);
|
||||
if (ret < 0)
|
||||
|
|
|
|||
|
|
@ -1,10 +1,9 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2016
|
||||
*
|
||||
* Author: Gerald Baeza <gerald.baeza@st.com>
|
||||
*
|
||||
* License terms: GNU General Public License (GPL), version 2
|
||||
*
|
||||
* Inspired by timer-stm32.c from Maxime Coquelin
|
||||
* pwm-atmel.c from Bo Shen
|
||||
*/
|
||||
|
|
@ -21,7 +20,7 @@
|
|||
|
||||
struct stm32_pwm {
|
||||
struct pwm_chip chip;
|
||||
struct device *dev;
|
||||
struct mutex lock; /* protect pwm config/enable */
|
||||
struct clk *clk;
|
||||
struct regmap *regmap;
|
||||
u32 max_arr;
|
||||
|
|
@ -214,9 +213,23 @@ static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm,
|
||||
struct pwm_state *state)
|
||||
{
|
||||
struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
|
||||
int ret;
|
||||
|
||||
/* protect common prescaler for all active channels */
|
||||
mutex_lock(&priv->lock);
|
||||
ret = stm32_pwm_apply(chip, pwm, state);
|
||||
mutex_unlock(&priv->lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct pwm_ops stm32pwm_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
.apply = stm32_pwm_apply,
|
||||
.apply = stm32_pwm_apply_locked,
|
||||
};
|
||||
|
||||
static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
|
||||
|
|
@ -336,6 +349,7 @@ static int stm32_pwm_probe(struct platform_device *pdev)
|
|||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
mutex_init(&priv->lock);
|
||||
priv->regmap = ddata->regmap;
|
||||
priv->clk = ddata->clk;
|
||||
priv->max_arr = ddata->max_arr;
|
||||
|
|
|
|||
|
|
@ -73,7 +73,6 @@ static const u32 prescaler_table[] = {
|
|||
|
||||
struct sun4i_pwm_data {
|
||||
bool has_prescaler_bypass;
|
||||
bool has_rdy;
|
||||
unsigned int npwm;
|
||||
};
|
||||
|
||||
|
|
@ -117,7 +116,8 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
|
|||
|
||||
val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
|
||||
|
||||
if ((val == PWM_PRESCAL_MASK) && sun4i_pwm->data->has_prescaler_bypass)
|
||||
if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
|
||||
sun4i_pwm->data->has_prescaler_bypass)
|
||||
prescaler = 1;
|
||||
else
|
||||
prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
|
||||
|
|
@ -130,7 +130,8 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
|
|||
else
|
||||
state->polarity = PWM_POLARITY_INVERSED;
|
||||
|
||||
if (val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))
|
||||
if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) ==
|
||||
BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))
|
||||
state->enabled = true;
|
||||
else
|
||||
state->enabled = false;
|
||||
|
|
@ -311,52 +312,37 @@ static const struct pwm_ops sun4i_pwm_ops = {
|
|||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static const struct sun4i_pwm_data sun4i_pwm_data_a10 = {
|
||||
static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
|
||||
.has_prescaler_bypass = false,
|
||||
.has_rdy = false,
|
||||
.npwm = 2,
|
||||
};
|
||||
|
||||
static const struct sun4i_pwm_data sun4i_pwm_data_a10s = {
|
||||
static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
|
||||
.has_prescaler_bypass = true,
|
||||
.has_rdy = true,
|
||||
.npwm = 2,
|
||||
};
|
||||
|
||||
static const struct sun4i_pwm_data sun4i_pwm_data_a13 = {
|
||||
static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
|
||||
.has_prescaler_bypass = true,
|
||||
.has_rdy = true,
|
||||
.npwm = 1,
|
||||
};
|
||||
|
||||
static const struct sun4i_pwm_data sun4i_pwm_data_a20 = {
|
||||
.has_prescaler_bypass = true,
|
||||
.has_rdy = true,
|
||||
.npwm = 2,
|
||||
};
|
||||
|
||||
static const struct sun4i_pwm_data sun4i_pwm_data_h3 = {
|
||||
.has_prescaler_bypass = true,
|
||||
.has_rdy = true,
|
||||
.npwm = 1,
|
||||
};
|
||||
|
||||
static const struct of_device_id sun4i_pwm_dt_ids[] = {
|
||||
{
|
||||
.compatible = "allwinner,sun4i-a10-pwm",
|
||||
.data = &sun4i_pwm_data_a10,
|
||||
.data = &sun4i_pwm_dual_nobypass,
|
||||
}, {
|
||||
.compatible = "allwinner,sun5i-a10s-pwm",
|
||||
.data = &sun4i_pwm_data_a10s,
|
||||
.data = &sun4i_pwm_dual_bypass,
|
||||
}, {
|
||||
.compatible = "allwinner,sun5i-a13-pwm",
|
||||
.data = &sun4i_pwm_data_a13,
|
||||
.data = &sun4i_pwm_single_bypass,
|
||||
}, {
|
||||
.compatible = "allwinner,sun7i-a20-pwm",
|
||||
.data = &sun4i_pwm_data_a20,
|
||||
.data = &sun4i_pwm_dual_bypass,
|
||||
}, {
|
||||
.compatible = "allwinner,sun8i-h3-pwm",
|
||||
.data = &sun4i_pwm_data_h3,
|
||||
.data = &sun4i_pwm_single_bypass,
|
||||
}, {
|
||||
/* sentinel */
|
||||
},
|
||||
|
|
|
|||
|
|
@ -273,7 +273,8 @@ static int pwm_export_child(struct device *parent, struct pwm_device *pwm)
|
|||
ret = device_register(&export->child);
|
||||
if (ret) {
|
||||
clear_bit(PWMF_EXPORTED, &pwm->flags);
|
||||
kfree(export);
|
||||
put_device(&export->child);
|
||||
export = NULL;
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue