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MIPS: document mixing "slightly different CCAs" 

Based on an email from Paul Burton, quoting section 4.8 "Cacheability and
Coherency Attributes and Access Types" of "MIPS Architecture Volume 1:
Introduction to the MIPS32 Architecture" (MD00080, revision 6.01).

Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Paul Burton <paul.burton@mips.com>
This commit is contained in:
Christoph Hellwig 2019-08-26 09:22:13 +02:00
parent 3e4e1d3fb8
commit db91427b65
1 changed files with 7 additions and 0 deletions
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arch/mips/Kconfig
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@ -1119,6 +1119,13 @@ config DMA_PERDEV_COHERENT
config DMA_NONCOHERENT config DMA_NONCOHERENT
bool bool
#
# MIPS allows mixing "slightly different" Cacheability and Coherency
# Attribute bits. It is believed that the uncached access through
# KSEG1 and the implementation specific "uncached accelerated" used
# by pgprot_writcombine can be mixed, and the latter sometimes provides
# significant advantages.
#
select ARCH_HAS_DMA_WRITE_COMBINE select ARCH_HAS_DMA_WRITE_COMBINE
select ARCH_HAS_SYNC_DMA_FOR_DEVICE select ARCH_HAS_SYNC_DMA_FOR_DEVICE
select ARCH_HAS_UNCACHED_SEGMENT select ARCH_HAS_UNCACHED_SEGMENT