wil6210: atomic I/O for the card memory
Introduce netdev IOCTLs, to be used by the debug tools. Allows to read/write single dword value or memory block, aligned to dword Different address modes supported: - BAR offset - Firmware "linker" address - target's AHB bus Signed-off-by: Vladimir Kondratiev <qca_vkondrat@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Vladimir Kondratiev
John W. Linville
parent
c33407a8c5
commit
dba4b74d2d
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@ -1611,6 +1611,7 @@ L: wil6210@qca.qualcomm.com
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S: Supported
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W: http://wireless.kernel.org/en/users/Drivers/wil6210
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F: drivers/net/wireless/ath/wil6210/
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F: include/uapi/linux/wil6210_uapi.h
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CARL9170 LINUX COMMUNITY WIRELESS DRIVER
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M: Christian Lamparter <chunkeey@googlemail.com>
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@ -10,6 +10,7 @@ wil6210-y += interrupt.o
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wil6210-y += txrx.o
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wil6210-y += debug.o
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wil6210-y += rx_reorder.o
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wil6210-y += ioctl.o
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wil6210-y += fw.o
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wil6210-$(CONFIG_WIL6210_TRACING) += trace.o
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wil6210-y += wil_platform.o
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@ -0,0 +1,173 @@
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/*
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* Copyright (c) 2014 Qualcomm Atheros, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <linux/uaccess.h>
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#include "wil6210.h"
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#include <uapi/linux/wil6210_uapi.h>
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#define wil_hex_dump_ioctl(prefix_str, buf, len) \
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print_hex_dump_debug("DBG[IOC ]" prefix_str, \
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DUMP_PREFIX_OFFSET, 16, 1, buf, len, true)
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#define wil_dbg_ioctl(wil, fmt, arg...) wil_dbg(wil, "DBG[IOC ]" fmt, ##arg)
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static void __iomem *wil_ioc_addr(struct wil6210_priv *wil, uint32_t addr,
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uint32_t size, enum wil_memio_op op)
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{
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void __iomem *a;
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u32 off;
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switch (op & wil_mmio_addr_mask) {
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case wil_mmio_addr_linker:
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a = wmi_buffer(wil, cpu_to_le32(addr));
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break;
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case wil_mmio_addr_ahb:
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a = wmi_addr(wil, addr);
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break;
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case wil_mmio_addr_bar:
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a = wmi_addr(wil, addr + WIL6210_FW_HOST_OFF);
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break;
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default:
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wil_err(wil, "Unsupported address mode, op = 0x%08x\n", op);
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return NULL;
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}
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off = a - wil->csr;
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if (size >= WIL6210_MEM_SIZE - off) {
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wil_err(wil, "Requested block does not fit into memory: "
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"off = 0x%08x size = 0x%08x\n", off, size);
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return NULL;
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}
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return a;
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}
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static int wil_ioc_memio_dword(struct wil6210_priv *wil, void __user *data)
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{
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struct wil_memio io;
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void __iomem *a;
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bool need_copy = false;
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if (copy_from_user(&io, data, sizeof(io)))
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return -EFAULT;
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wil_dbg_ioctl(wil, "IO: addr = 0x%08x val = 0x%08x op = 0x%08x\n",
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io.addr, io.val, io.op);
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a = wil_ioc_addr(wil, io.addr, sizeof(u32), io.op);
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if (!a) {
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wil_err(wil, "invalid address 0x%08x, op = 0x%08x\n", io.addr,
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io.op);
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return -EINVAL;
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}
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/* operation */
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switch (io.op & wil_mmio_op_mask) {
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case wil_mmio_read:
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io.val = ioread32(a);
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need_copy = true;
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break;
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case wil_mmio_write:
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iowrite32(io.val, a);
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wmb(); /* make sure write propagated to HW */
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break;
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default:
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wil_err(wil, "Unsupported operation, op = 0x%08x\n", io.op);
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return -EINVAL;
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}
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if (need_copy) {
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wil_dbg_ioctl(wil, "IO done: addr = 0x%08x"
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" val = 0x%08x op = 0x%08x\n",
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io.addr, io.val, io.op);
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if (copy_to_user(data, &io, sizeof(io)))
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return -EFAULT;
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}
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return 0;
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}
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static int wil_ioc_memio_block(struct wil6210_priv *wil, void __user *data)
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{
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struct wil_memio_block io;
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void *block;
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void __iomem *a;
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int rc = 0;
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if (copy_from_user(&io, data, sizeof(io)))
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return -EFAULT;
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wil_dbg_ioctl(wil, "IO: addr = 0x%08x size = 0x%08x op = 0x%08x\n",
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io.addr, io.size, io.op);
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/* size */
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if (io.size % 4) {
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wil_err(wil, "size is not multiple of 4: 0x%08x\n", io.size);
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return -EINVAL;
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}
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a = wil_ioc_addr(wil, io.addr, io.size, io.op);
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if (!a) {
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wil_err(wil, "invalid address 0x%08x, op = 0x%08x\n", io.addr,
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io.op);
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return -EINVAL;
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}
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block = kmalloc(io.size, GFP_USER);
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if (!block)
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return -ENOMEM;
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/* operation */
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switch (io.op & wil_mmio_op_mask) {
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case wil_mmio_read:
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wil_memcpy_fromio_32(block, a, io.size);
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wil_hex_dump_ioctl("Read ", block, io.size);
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if (copy_to_user(io.block, block, io.size)) {
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rc = -EFAULT;
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goto out_free;
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}
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break;
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case wil_mmio_write:
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if (copy_from_user(block, io.block, io.size)) {
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rc = -EFAULT;
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goto out_free;
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}
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wil_memcpy_toio_32(a, block, io.size);
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wmb(); /* make sure write propagated to HW */
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wil_hex_dump_ioctl("Write ", block, io.size);
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break;
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default:
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wil_err(wil, "Unsupported operation, op = 0x%08x\n", io.op);
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rc = -EINVAL;
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break;
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}
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out_free:
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kfree(block);
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return rc;
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}
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int wil_ioctl(struct wil6210_priv *wil, void __user *data, int cmd)
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{
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switch (cmd) {
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case WIL_IOCTL_MEMIO:
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return wil_ioc_memio_dword(wil, data);
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case WIL_IOCTL_MEMIO_BLOCK:
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return wil_ioc_memio_block(wil, data);
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default:
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wil_dbg_ioctl(wil, "Unsupported IOCTL 0x%04x\n", cmd);
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return -ENOIOCTLCMD;
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}
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}
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@ -52,6 +52,17 @@ static int wil_change_mtu(struct net_device *ndev, int new_mtu)
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return 0;
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}
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static int wil_do_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
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{
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struct wil6210_priv *wil = ndev_to_wil(ndev);
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int ret = wil_ioctl(wil, ifr->ifr_data, cmd);
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wil_dbg_misc(wil, "ioctl(0x%04x) -> %d\n", cmd, ret);
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return ret;
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}
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static const struct net_device_ops wil_netdev_ops = {
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.ndo_open = wil_open,
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.ndo_stop = wil_stop,
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@ -59,6 +70,7 @@ static const struct net_device_ops wil_netdev_ops = {
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.ndo_set_mac_address = eth_mac_addr,
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.ndo_validate_addr = eth_validate_addr,
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.ndo_change_mtu = wil_change_mtu,
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.ndo_do_ioctl = wil_do_ioctl,
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};
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static int wil6210_netdev_poll_rx(struct napi_struct *napi, int budget)
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@ -595,5 +595,7 @@ void wil6210_unmask_irq_rx(struct wil6210_priv *wil);
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int wil_iftype_nl2wmi(enum nl80211_iftype type);
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int wil_ioctl(struct wil6210_priv *wil, void __user *data, int cmd);
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int wil_request_firmware(struct wil6210_priv *wil, const char *name);
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#endif /* __WIL6210_H__ */
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@ -0,0 +1,87 @@
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/*
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* Copyright (c) 2014 Qualcomm Atheros, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef __WIL6210_UAPI_H__
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#define __WIL6210_UAPI_H__
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#if !defined(__KERNEL__)
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#define __user
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#endif
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#include <linux/sockios.h>
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/* Numbers SIOCDEVPRIVATE and SIOCDEVPRIVATE + 1
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* are used by Android devices to implement PNO (preferred network offload).
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* Albeit it is temporary solution, use different numbers to avoid conflicts
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*/
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/**
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* Perform 32-bit I/O operation to the card memory
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*
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* User code should arrange data in memory like this:
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*
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* struct wil_memio io;
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* struct ifreq ifr = {
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* .ifr_data = &io,
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* };
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*/
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#define WIL_IOCTL_MEMIO (SIOCDEVPRIVATE + 2)
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/**
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* Perform block I/O operation to the card memory
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*
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* User code should arrange data in memory like this:
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*
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* void *buf;
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* struct wil_memio_block io = {
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* .block = buf,
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* };
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* struct ifreq ifr = {
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* .ifr_data = &io,
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* };
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*/
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#define WIL_IOCTL_MEMIO_BLOCK (SIOCDEVPRIVATE + 3)
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/**
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* operation to perform
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*
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* @wil_mmio_op_mask - bits defining operation,
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* @wil_mmio_addr_mask - bits defining addressing mode
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*/
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enum wil_memio_op {
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wil_mmio_read = 0,
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wil_mmio_write = 1,
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wil_mmio_op_mask = 0xff,
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wil_mmio_addr_linker = 0 << 8,
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wil_mmio_addr_ahb = 1 << 8,
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wil_mmio_addr_bar = 2 << 8,
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wil_mmio_addr_mask = 0xff00,
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};
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struct wil_memio {
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uint32_t op; /* enum wil_memio_op */
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uint32_t addr; /* should be 32-bit aligned */
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uint32_t val;
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};
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struct wil_memio_block {
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uint32_t op; /* enum wil_memio_op */
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uint32_t addr; /* should be 32-bit aligned */
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uint32_t size; /* should be multiple of 4 */
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void __user *block; /* block address */
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};
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#endif /* __WIL6210_UAPI_H__ */
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