x86/events/amd/iommu: Clean up perf_iommu_read()
Fix coding style and use GENMASK_ULL(). Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Jörg Rödel <joro@8bytes.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Cc: iommu@lists.linux-foundation.org Link: http://lkml.kernel.org/r/1487926102-13073-4-git-send-email-Suravee.Suthikulpanit@amd.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -320,9 +320,7 @@ static void perf_iommu_start(struct perf_event *event, int flags)
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static void perf_iommu_read(struct perf_event *event)
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{
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u64 count = 0ULL;
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u64 prev_raw_count = 0ULL;
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u64 delta = 0ULL;
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u64 count, prev, delta;
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struct hw_perf_event *hwc = &event->hw;
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amd_iommu_pc_get_set_reg_val(_GET_DEVID(event),
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@ -330,18 +328,16 @@ static void perf_iommu_read(struct perf_event *event)
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IOMMU_PC_COUNTER_REG, &count, false);
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/* IOMMU pc counter register is only 48 bits */
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count &= 0xFFFFFFFFFFFFULL;
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count &= GENMASK_ULL(47, 0);
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prev_raw_count = local64_read(&hwc->prev_count);
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if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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count) != prev_raw_count)
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prev = local64_read(&hwc->prev_count);
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if (local64_cmpxchg(&hwc->prev_count, prev, count) != prev)
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return;
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/* Handling 48-bit counter overflowing */
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delta = (count << COUNTER_SHIFT) - (prev_raw_count << COUNTER_SHIFT);
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/* Handle 48-bit counter overflow */
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delta = (count << COUNTER_SHIFT) - (prev << COUNTER_SHIFT);
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delta >>= COUNTER_SHIFT;
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local64_add(delta, &event->count);
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}
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static void perf_iommu_stop(struct perf_event *event, int flags)
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