MIPS: OCTEON: Update octeon-model.h code for new SoCs.
Add coverage for OCTEON III models. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8942/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney
Ralf Baechle
parent
e3d0ead59f
commit
debe6a623d
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@ -276,7 +276,7 @@ void __init plat_swiotlb_setup(void)
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continue;
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/* These addresses map low for PCI. */
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if (e->addr > 0x410000000ull && !OCTEON_IS_MODEL(OCTEON_CN6XXX))
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if (e->addr > 0x410000000ull && !OCTEON_IS_OCTEON2())
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continue;
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addr_size += e->size;
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@ -308,7 +308,7 @@ void __init plat_swiotlb_setup(void)
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#endif
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#ifdef CONFIG_USB_OCTEON_OHCI
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/* OCTEON II ohci is only 32-bit. */
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && max_addr >= 0x100000000ul)
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if (OCTEON_IS_OCTEON2() && max_addr >= 0x100000000ul)
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swiotlbsize = 64 * (1<<20);
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#endif
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swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT;
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@ -767,7 +767,7 @@ enum cvmx_helper_board_usb_clock_types __cvmx_helper_board_usb_get_clock_type(vo
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break;
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}
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/* Most boards except NIC10e use a 12MHz crystal */
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if (OCTEON_IS_MODEL(OCTEON_FAM_2))
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if (OCTEON_IS_OCTEON2())
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return USB_CLOCK_TYPE_CRYSTAL_12;
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return USB_CLOCK_TYPE_REF_48;
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}
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@ -1210,7 +1210,7 @@ static void __init octeon_irq_init_ciu(void)
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if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
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OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
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OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) ||
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OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
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OCTEON_IS_OCTEON2() || OCTEON_IS_OCTEON3()) {
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chip = &octeon_irq_chip_ciu_v2;
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chip_mbox = &octeon_irq_chip_ciu_mbox_v2;
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chip_wd = &octeon_irq_chip_ciu_wd_v2;
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@ -655,7 +655,7 @@ void __init prom_init(void)
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sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
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sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
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if (OCTEON_IS_OCTEON2() || OCTEON_IS_OCTEON3()) {
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/* I/O clock runs at a different rate than the CPU. */
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union cvmx_mio_rst_boot rst_boot;
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rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
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@ -45,6 +45,7 @@
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*/
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#define OCTEON_FAMILY_MASK 0x00ffff00
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#define OCTEON_PRID_MASK 0x00ffffff
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/* Flag bits in top byte */
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/* Ignores revision in model checks */
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@ -63,11 +64,52 @@
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#define OM_MATCH_6XXX_FAMILY_MODELS 0x40000000
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/* Match all cnf7XXX Octeon models. */
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#define OM_MATCH_F7XXX_FAMILY_MODELS 0x80000000
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/* Match all cn7XXX Octeon models. */
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#define OM_MATCH_7XXX_FAMILY_MODELS 0x10000000
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#define OM_MATCH_FAMILY_MODELS (OM_MATCH_5XXX_FAMILY_MODELS | \
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OM_MATCH_6XXX_FAMILY_MODELS | \
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OM_MATCH_F7XXX_FAMILY_MODELS | \
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OM_MATCH_7XXX_FAMILY_MODELS)
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/*
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* CN7XXX models with new revision encoding
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*/
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#define OCTEON_CN73XX_PASS1_0 0x000d9700
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#define OCTEON_CN73XX (OCTEON_CN73XX_PASS1_0 | OM_IGNORE_REVISION)
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#define OCTEON_CN73XX_PASS1_X (OCTEON_CN73XX_PASS1_0 | \
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OM_IGNORE_MINOR_REVISION)
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#define OCTEON_CN70XX_PASS1_0 0x000d9600
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#define OCTEON_CN70XX_PASS1_1 0x000d9601
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#define OCTEON_CN70XX_PASS1_2 0x000d9602
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#define OCTEON_CN70XX_PASS2_0 0x000d9608
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#define OCTEON_CN70XX (OCTEON_CN70XX_PASS1_0 | OM_IGNORE_REVISION)
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#define OCTEON_CN70XX_PASS1_X (OCTEON_CN70XX_PASS1_0 | \
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OM_IGNORE_MINOR_REVISION)
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#define OCTEON_CN70XX_PASS2_X (OCTEON_CN70XX_PASS2_0 | \
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OM_IGNORE_MINOR_REVISION)
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#define OCTEON_CN71XX OCTEON_CN70XX
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#define OCTEON_CN78XX_PASS1_0 0x000d9500
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#define OCTEON_CN78XX_PASS1_1 0x000d9501
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#define OCTEON_CN78XX_PASS2_0 0x000d9508
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#define OCTEON_CN78XX (OCTEON_CN78XX_PASS1_0 | OM_IGNORE_REVISION)
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#define OCTEON_CN78XX_PASS1_X (OCTEON_CN78XX_PASS1_0 | \
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OM_IGNORE_MINOR_REVISION)
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#define OCTEON_CN78XX_PASS2_X (OCTEON_CN78XX_PASS2_0 | \
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OM_IGNORE_MINOR_REVISION)
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#define OCTEON_CN76XX (0x000d9540 | OM_CHECK_SUBMODEL)
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/*
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* CNF7XXX models with new revision encoding
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*/
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#define OCTEON_CNF71XX_PASS1_0 0x000d9400
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#define OCTEON_CNF71XX_PASS1_1 0x000d9401
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#define OCTEON_CNF71XX (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_REVISION)
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#define OCTEON_CNF71XX_PASS1_X (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
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@ -79,6 +121,8 @@
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#define OCTEON_CN68XX_PASS1_1 0x000d9101
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#define OCTEON_CN68XX_PASS1_2 0x000d9102
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#define OCTEON_CN68XX_PASS2_0 0x000d9108
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#define OCTEON_CN68XX_PASS2_1 0x000d9109
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#define OCTEON_CN68XX_PASS2_2 0x000d910a
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#define OCTEON_CN68XX (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_REVISION)
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#define OCTEON_CN68XX_PASS1_X (OCTEON_CN68XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
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@ -104,11 +148,18 @@
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#define OCTEON_CN63XX_PASS1_X (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
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#define OCTEON_CN63XX_PASS2_X (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
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/* CN62XX is same as CN63XX with 1 MB cache */
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#define OCTEON_CN62XX OCTEON_CN63XX
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#define OCTEON_CN61XX_PASS1_0 0x000d9300
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#define OCTEON_CN61XX_PASS1_1 0x000d9301
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#define OCTEON_CN61XX (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_REVISION)
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#define OCTEON_CN61XX_PASS1_X (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
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/* CN60XX is same as CN61XX with 512 KB cache */
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#define OCTEON_CN60XX OCTEON_CN61XX
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/*
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* CN5XXX models with new revision encoding
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*/
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@ -120,7 +171,7 @@
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#define OCTEON_CN58XX_PASS2_2 0x000d030a
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#define OCTEON_CN58XX_PASS2_3 0x000d030b
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#define OCTEON_CN58XX (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION)
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#define OCTEON_CN58XX (OCTEON_CN58XX_PASS2_0 | OM_IGNORE_REVISION)
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#define OCTEON_CN58XX_PASS1_X (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
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#define OCTEON_CN58XX_PASS2_X (OCTEON_CN58XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
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#define OCTEON_CN58XX_PASS1 OCTEON_CN58XX_PASS1_X
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@ -217,12 +268,10 @@
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#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION)
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#define OCTEON_CN5XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS)
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#define OCTEON_CN6XXX (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS)
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/* These are used to cover entire families of OCTEON processors */
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#define OCTEON_FAM_1 (OCTEON_CN3XXX)
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#define OCTEON_FAM_PLUS (OCTEON_CN5XXX)
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#define OCTEON_FAM_1_PLUS (OCTEON_FAM_PLUS | OM_MATCH_PREVIOUS_MODELS)
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#define OCTEON_FAM_2 (OCTEON_CN6XXX)
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#define OCTEON_CNF7XXX (OCTEON_CNF71XX_PASS1_0 | \
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OM_MATCH_F7XXX_FAMILY_MODELS)
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#define OCTEON_CN7XXX (OCTEON_CN78XX_PASS1_0 | \
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OM_MATCH_7XXX_FAMILY_MODELS)
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/* The revision byte (low byte) has two different encodings.
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* CN3XXX:
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@ -232,7 +281,7 @@
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* <4>: alternate package
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* <3:0>: revision
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*
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* CN5XXX:
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* CN5XXX and older models:
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*
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* bits
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* <7>: reserved (0)
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@ -251,17 +300,21 @@
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/* CN5XXX and later use different layout of bits in the revision ID field */
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#define OCTEON_58XX_FAMILY_MASK OCTEON_38XX_FAMILY_MASK
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#define OCTEON_58XX_FAMILY_REV_MASK 0x00ffff3f
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#define OCTEON_58XX_MODEL_MASK 0x00ffffc0
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#define OCTEON_58XX_MODEL_MASK 0x00ffff40
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#define OCTEON_58XX_MODEL_REV_MASK (OCTEON_58XX_FAMILY_REV_MASK | OCTEON_58XX_MODEL_MASK)
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#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK & 0x00fffff8)
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#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK & 0x00ffff38)
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#define OCTEON_5XXX_MODEL_MASK 0x00ff0fc0
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/* forward declarations */
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static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
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static inline uint64_t cvmx_read_csr(uint64_t csr_addr);
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#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
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/*
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* __OCTEON_IS_MODEL_COMPILE__(arg_model, chip_model)
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* returns true if chip_model is identical or belong to the OCTEON
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* model group specified in arg_model.
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*/
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/* NOTE: This for internal use only! */
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#define __OCTEON_IS_MODEL_COMPILE__(arg_model, chip_model) \
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((((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) && ( \
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@ -286,11 +339,18 @@ static inline uint64_t cvmx_read_csr(uint64_t csr_addr);
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((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_REVISION) \
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&& __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_MASK)) || \
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((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL) \
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&& __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_REV_MASK)) || \
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&& __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MASK)) || \
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((((arg_model) & (OM_MATCH_5XXX_FAMILY_MODELS)) == OM_MATCH_5XXX_FAMILY_MODELS) \
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&& ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0)) || \
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&& ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CN58XX_PASS1_0) \
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&& ((chip_model & OCTEON_PRID_MASK) < OCTEON_CN63XX_PASS1_0)) || \
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((((arg_model) & (OM_MATCH_6XXX_FAMILY_MODELS)) == OM_MATCH_6XXX_FAMILY_MODELS) \
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&& ((chip_model) >= OCTEON_CN63XX_PASS1_0)) || \
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&& ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CN63XX_PASS1_0) \
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&& ((chip_model & OCTEON_PRID_MASK) < OCTEON_CNF71XX_PASS1_0)) || \
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((((arg_model) & (OM_MATCH_F7XXX_FAMILY_MODELS)) == OM_MATCH_F7XXX_FAMILY_MODELS) \
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&& ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CNF71XX_PASS1_0) \
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&& ((chip_model & OCTEON_PRID_MASK) < OCTEON_CN78XX_PASS1_0)) || \
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((((arg_model) & (OM_MATCH_7XXX_FAMILY_MODELS)) == OM_MATCH_7XXX_FAMILY_MODELS) \
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&& ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CN78XX_PASS1_0)) || \
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((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
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&& (((chip_model) & OCTEON_58XX_MODEL_MASK) < ((arg_model) & OCTEON_58XX_MODEL_MASK))) \
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)))
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@ -300,14 +360,6 @@ static inline int __octeon_is_model_runtime__(uint32_t model)
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{
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uint32_t cpuid = cvmx_get_proc_id();
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/*
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* Check for special case of mismarked 3005 samples. We only
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* need to check if the sub model isn't being ignored
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*/
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if ((model & OM_CHECK_SUBMODEL) == OM_CHECK_SUBMODEL) {
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if (cpuid == OCTEON_CN3010_PASS1 && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34)))
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cpuid |= 0x10;
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}
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return __OCTEON_IS_MODEL_COMPILE__(model, cpuid);
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}
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@ -326,10 +378,21 @@ static inline int __octeon_is_model_runtime__(uint32_t model)
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#define OCTEON_IS_COMMON_BINARY() 1
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#undef OCTEON_MODEL
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#define OCTEON_IS_OCTEON1() OCTEON_IS_MODEL(OCTEON_CN3XXX)
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#define OCTEON_IS_OCTEONPLUS() OCTEON_IS_MODEL(OCTEON_CN5XXX)
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#define OCTEON_IS_OCTEON2() \
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(OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))
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#define OCTEON_IS_OCTEON3() OCTEON_IS_MODEL(OCTEON_CN7XXX)
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#define OCTEON_IS_OCTEON1PLUS() (OCTEON_IS_OCTEON1() || OCTEON_IS_OCTEONPLUS())
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const char *__init octeon_model_get_string(uint32_t chip_id);
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/*
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* Return the octeon family, i.e., ProcessorID of the PrID register.
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*
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* @return the octeon family on success, ((unint32_t)-1) on error.
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*/
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static inline uint32_t cvmx_get_octeon_family(void)
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{
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