scsi: qla2xxx: Added change to enable ZIO for FC-NVMe devices
Add support to the driver to set the exchange threshold value for the number of outstanding AENs. Signed-off-by: Duane Grigsby <duane.grigsby@cavium.com> Signed-off-by: Darren Trapp <darren.trapp@cavium.com> Signed-off-by: Anil Gurumurthy <anil.gurumurthy@cavium.com> Signed-off-by: Himanshu Madhani <himanshu.madhani@cavium.com> Reviewed-by: Johannes Thumshirn <jthumshirn@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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@ -14,7 +14,7 @@
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* | Module Init and Probe | 0x0193 | 0x0146 |
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* | | | 0x015b-0x0160 |
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* | | | 0x016e |
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* | Mailbox commands | 0x1199 | 0x1193 |
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* | Mailbox commands | 0x1205 | 0x11a2-0x11ff |
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* | Device Discovery | 0x2134 | 0x210e-0x2116 |
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* | | | 0x211a |
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* | | | 0x211c-0x2128 |
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@ -977,6 +977,7 @@ struct mbx_cmd_32 {
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#define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
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#define MBC_RESET 0x18 /* Reset. */
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#define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
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#define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */
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#define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
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#define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
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#define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
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@ -4017,6 +4018,9 @@ struct qla_hw_data {
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struct qlt_hw_data tgt;
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int allow_cna_fw_dump;
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atomic_t nvme_active_aen_cnt;
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uint16_t nvme_last_rptd_aen; /* Last recorded aen count */
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};
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/*
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@ -4089,6 +4093,7 @@ typedef struct scsi_qla_host {
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#define FX00_CRITEMP_RECOVERY 25
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#define FX00_HOST_INFO_RESEND 26
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#define QPAIR_ONLINE_CHECK_NEEDED 27
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#define SET_ZIO_THRESHOLD_NEEDED 28
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unsigned long pci_flags;
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#define PFLG_DISCONNECTED 0 /* PCI device removed */
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@ -484,6 +484,9 @@ int qla24xx_gidlist_wait(struct scsi_qla_host *, void *, dma_addr_t,
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int __qla24xx_parse_gpdb(struct scsi_qla_host *, fc_port_t *,
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struct port_database_24xx *);
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extern int qla27xx_get_zio_threshold(scsi_qla_host_t *, uint16_t *);
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extern int qla27xx_set_zio_threshold(scsi_qla_host_t *, uint16_t);
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/*
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* Global Function Prototypes in qla_isr.c source file.
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*/
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@ -1823,7 +1823,7 @@ qla24xx_nvme_iocb_entry(scsi_qla_host_t *vha, struct req_que *req, void *tsk)
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nvme = &sp->u.iocb_cmd;
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if (unlikely(nvme->u.nvme.aen_op))
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atomic_dec(&sp->vha->nvme_active_aen_cnt);
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atomic_dec(&sp->vha->hw->nvme_active_aen_cnt);
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/*
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* State flags: Bit 6 and 0.
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@ -947,20 +947,12 @@ qla2x00_get_fw_version(scsi_qla_host_t *vha)
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"%s: Firmware supports Exchange Offload 0x%x\n",
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__func__, ha->fw_attributes_h);
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/* bit 26 of fw_attributes */
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if ((ha->fw_attributes_h & 0x400) && ql2xnvmeenable) {
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struct init_cb_24xx *icb;
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icb = (struct init_cb_24xx *)ha->init_cb;
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/*
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* fw supports nvme and driver load
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* parameter requested nvme
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*/
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/*
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* FW supports nvme and driver load parameter requested nvme.
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* BIT 26 of fw_attributes indicates NVMe support.
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*/
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if ((ha->fw_attributes_h & 0x400) && ql2xnvmeenable)
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vha->flags.nvme_enabled = 1;
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icb->firmware_options_2 &= cpu_to_le32(~0xf);
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ha->zio_mode = 0;
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ha->zio_timer = 0;
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}
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}
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@ -6085,3 +6077,56 @@ int qla24xx_gidlist_wait(struct scsi_qla_host *vha,
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done:
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return rval;
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}
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int qla27xx_set_zio_threshold(scsi_qla_host_t *vha, uint16_t value)
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{
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int rval;
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mbx_cmd_t mc;
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mbx_cmd_t *mcp = &mc;
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ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1200,
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"Entered %s\n", __func__);
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memset(mcp->mb, 0 , sizeof(mcp->mb));
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mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD;
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mcp->mb[1] = cpu_to_le16(1);
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mcp->mb[2] = cpu_to_le16(value);
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mcp->out_mb = MBX_2 | MBX_1 | MBX_0;
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mcp->in_mb = MBX_2 | MBX_0;
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mcp->tov = MBX_TOV_SECONDS;
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mcp->flags = 0;
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rval = qla2x00_mailbox_command(vha, mcp);
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ql_dbg(ql_dbg_mbx, vha, 0x1201, "%s %x\n",
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(rval != QLA_SUCCESS) ? "Failed" : "Done", rval);
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return rval;
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}
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int qla27xx_get_zio_threshold(scsi_qla_host_t *vha, uint16_t *value)
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{
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int rval;
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mbx_cmd_t mc;
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mbx_cmd_t *mcp = &mc;
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ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1203,
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"Entered %s\n", __func__);
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memset(mcp->mb, 0, sizeof(mcp->mb));
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mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD;
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mcp->mb[1] = cpu_to_le16(0);
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mcp->out_mb = MBX_1 | MBX_0;
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mcp->in_mb = MBX_2 | MBX_0;
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mcp->tov = MBX_TOV_SECONDS;
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mcp->flags = 0;
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rval = qla2x00_mailbox_command(vha, mcp);
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if (rval == QLA_SUCCESS)
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*value = mc.mb[2];
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ql_dbg(ql_dbg_mbx, vha, 0x1205, "%s %x\n",
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(rval != QLA_SUCCESS) ? "Failed" : "Done", rval);
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return rval;
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}
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@ -305,6 +305,7 @@ static int qla2x00_start_nvme_mq(srb_t *sp)
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uint16_t avail_dsds;
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uint32_t *cur_dsd;
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struct req_que *req = NULL;
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struct rsp_que *rsp = NULL;
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struct scsi_qla_host *vha = sp->fcport->vha;
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struct qla_hw_data *ha = vha->hw;
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struct qla_qpair *qpair = sp->qpair;
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@ -313,13 +314,15 @@ static int qla2x00_start_nvme_mq(srb_t *sp)
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struct nvmefc_fcp_req *fd = nvme->u.nvme.desc;
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uint32_t rval = QLA_SUCCESS;
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/* Setup qpair pointers */
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req = qpair->req;
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tot_dsds = fd->sg_cnt;
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/* Acquire qpair specific lock */
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spin_lock_irqsave(&qpair->qp_lock, flags);
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/* Setup qpair pointers */
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req = qpair->req;
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rsp = qpair->rsp;
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/* Check for room in outstanding command list. */
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handle = req->current_outstanding_cmd;
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for (index = 1; index < req->num_outstanding_cmds; index++) {
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@ -354,7 +357,7 @@ static int qla2x00_start_nvme_mq(srb_t *sp)
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struct nvme_fc_cmd_iu *cmd = fd->cmdaddr;
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if (cmd->sqe.common.opcode == nvme_admin_async_event) {
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nvme->u.nvme.aen_op = 1;
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atomic_inc(&vha->nvme_active_aen_cnt);
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atomic_inc(&vha->hw->nvme_active_aen_cnt);
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}
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}
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@ -467,6 +470,11 @@ static int qla2x00_start_nvme_mq(srb_t *sp)
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/* Set chip new ring index. */
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WRT_REG_DWORD(req->req_q_in, req->ring_index);
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/* Manage unprocessed RIO/ZIO commands in response queue. */
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if (vha->flags.process_response_queue &&
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rsp->ring_ptr->signature != RESPONSE_PROCESSED)
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qla24xx_process_response_queue(vha, rsp);
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queuing_error:
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spin_unlock_irqrestore(&qpair->qp_lock, flags);
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return rval;
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@ -2751,6 +2751,7 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
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spin_lock_init(&ha->tgt.sess_lock);
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spin_lock_init(&ha->tgt.atio_lock);
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atomic_set(&ha->nvme_active_aen_cnt, 0);
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/* Clear our data area */
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ha->bars = bars;
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@ -5828,6 +5829,17 @@ qla2x00_do_dpc(void *data)
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mutex_unlock(&ha->mq_lock);
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}
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if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, &base_vha->dpc_flags)) {
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ql_log(ql_log_info, base_vha, 0xffffff,
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"nvme: SET ZIO Activity exchange threshold to %d.\n",
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ha->nvme_last_rptd_aen);
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if (qla27xx_set_zio_threshold(base_vha, ha->nvme_last_rptd_aen)) {
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ql_log(ql_log_info, base_vha, 0xffffff,
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"nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
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ha->nvme_last_rptd_aen);
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}
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}
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if (!IS_QLAFX00(ha))
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qla2x00_do_dpc_all_vps(base_vha);
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* FC-NVME
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* see if the active AEN count has changed from what was last reported.
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*/
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if (atomic_read(&vha->nvme_active_aen_cnt) != vha->nvme_last_rptd_aen) {
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vha->nvme_last_rptd_aen =
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atomic_read(&vha->nvme_active_aen_cnt);
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if (!vha->vp_idx &&
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atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen &&
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ha->zio_mode == QLA_ZIO_MODE_6) {
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ql_log(ql_log_info, vha, 0x3002,
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"reporting new aen count of %d to the fw\n",
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vha->nvme_last_rptd_aen);
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"nvme: Sched: Set ZIO exchange threshold to %d.\n",
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ha->nvme_last_rptd_aen);
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ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
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set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
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start_dpc++;
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}
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/* Schedule the DPC routine if needed */
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