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Merge (part of) tag 'omap-for-v3.19/hwmod-and-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc 

SoC related changes for omaps including hwmod clean-up for
DSS, and hwmod data for more UARTs and ADC. Also few defconfig
changes to enable devices found on am335x and am437x.

[arnd: I removed the defconfig changes from the branch in order
 to cherry-pick them onto the next/defconfig branch, but I did
 not change the other commits]

* commit '29c4ce17bcad':
  ARM: dts: cm-t3x30: add keypad support
  ARM: OMAP2+: hwmod: AM43x: add hwmod support for ADC on AM43xx
  ARM: DRA7: hwmod data: Add missing UART hwmod data
  ARM: dts: omap4.dtsi: remove dss_fck
  ARM: OMAP4: fix RFBI iclk
  ARM: OMAP4: hwmod: use MODULEMODE properly
  ARM: OMAP4: hwmod: set DSS submodule parent hwmods
  ARM: OMAP5: hwmod: set DSS submodule parent hwmods
  ARM: OMAP2+: hwmod: add parent_hwmod support

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2014-11-28 14:50:13 +01:00
parent 09ffd948a0 29c4ce17bc
commit df717a58a3
9 changed files with 208 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
arch/arm/boot/dts/omap3-cm-t3x30.dtsi
View File

@ -64,6 +64,7 @@ twl: twl@48 {
#include "twl4030.dtsi"
#include "twl4030_omap3.dtsi"
#include <dt-bindings/input/input.h>
&mmc1 {
vmmc-supply = <&vmmc1>;
@ -75,6 +76,22 @@ &twl_gpio {
ti,pullups = <0x000001>;
};
&twl_keypad {
linux,keymap = <
MATRIX_KEY(0x00, 0x01, KEY_A)
MATRIX_KEY(0x00, 0x02, KEY_B)
MATRIX_KEY(0x00, 0x03, KEY_LEFT)
MATRIX_KEY(0x01, 0x01, KEY_UP)
MATRIX_KEY(0x01, 0x02, KEY_ENTER)
MATRIX_KEY(0x01, 0x03, KEY_DOWN)
MATRIX_KEY(0x02, 0x01, KEY_RIGHT)
MATRIX_KEY(0x02, 0x02, KEY_C)
MATRIX_KEY(0x02, 0x03, KEY_D)
>;
};
&hsusb1_phy {
reset-gpios = <&twl_gpio 6 GPIO_ACTIVE_LOW>;
};

2
arch/arm/boot/dts/omap4.dtsi
View File

@ -895,7 +895,7 @@ rfbi: encoder@58002000 {
reg = <0x58002000 0x1000>;
status = "disabled";
ti,hwmods = "dss_rfbi";
clocks = <&dss_dss_clk>, <&dss_fck>;
clocks = <&dss_dss_clk>, <&l3_div_ck>;
clock-names = "fck", "ick";
};

8
arch/arm/boot/dts/omap44xx-clocks.dtsi
View File

@ -1018,14 +1018,6 @@ dss_48mhz_clk: dss_48mhz_clk {
reg = <0x1120>;
};
dss_fck: dss_fck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3_div_ck>;
ti,bit-shift = <1>;
reg = <0x1120>;
};
fdif_fck: fdif_fck {
#clock-cells = <0>;
compatible = "ti,divider-clock";

22
arch/arm/mach-omap2/omap_hwmod.c
View File

@ -2635,11 +2635,33 @@ static int __init _setup(struct omap_hwmod *oh, void *data)
if (oh->_state != _HWMOD_STATE_INITIALIZED)
return 0;
if (oh->parent_hwmod) {
int r;
r = _enable(oh->parent_hwmod);
WARN(r, "hwmod: %s: setup: failed to enable parent hwmod %s\n",
oh->name, oh->parent_hwmod->name);
}
_setup_iclk_autoidle(oh);
if (!_setup_reset(oh))
_setup_postsetup(oh);
if (oh->parent_hwmod) {
u8 postsetup_state;
postsetup_state = oh->parent_hwmod->_postsetup_state;
if (postsetup_state == _HWMOD_STATE_IDLE)
_idle(oh->parent_hwmod);
else if (postsetup_state == _HWMOD_STATE_DISABLED)
_shutdown(oh->parent_hwmod);
else if (postsetup_state != _HWMOD_STATE_ENABLED)
WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n",
oh->parent_hwmod->name, postsetup_state);
}
return 0;
}

8
arch/arm/mach-omap2/omap_hwmod.h
View File

@ -633,6 +633,7 @@ struct omap_hwmod_link {
* @flags: hwmod flags (documented below)
* @_lock: spinlock serializing operations on this hwmod
* @node: list node for hwmod list (internal use)
* @parent_hwmod: (temporary) a pointer to the hierarchical parent of this hwmod
*
* @main_clk refers to this module's "main clock," which for our
* purposes is defined as "the functional clock needed for register
@ -643,6 +644,12 @@ struct omap_hwmod_link {
* the omap_hwmod code and should not be set during initialization.
*
* @masters and @slaves are now deprecated.
*
* @parent_hwmod is temporary; there should be no need for it, as this
* information should already be expressed in the OCP interface
* structures. @parent_hwmod is present as a workaround until we improve
* handling for hwmods with multiple parents (e.g., OMAP4+ DSS with
* multiple register targets across different interconnects).
*/
struct omap_hwmod {
const char *name;
@ -680,6 +687,7 @@ struct omap_hwmod {
u8 _int_flags;
u8 _state;
u8 _postsetup_state;
struct omap_hwmod *parent_hwmod;
};
struct omap_hwmod *omap_hwmod_lookup(const char *name);

39
arch/arm/mach-omap2/omap_hwmod_43xx_data.c
View File

@ -417,6 +417,37 @@ static struct omap_hwmod am43xx_qspi_hwmod = {
},
};
/*
* 'adc/tsc' class
* TouchScreen Controller (Analog-To-Digital Converter)
*/
static struct omap_hwmod_class_sysconfig am43xx_adc_tsc_sysc = {
.rev_offs = 0x00,
.sysc_offs = 0x10,
.sysc_flags = SYSC_HAS_SIDLEMODE,
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class am43xx_adc_tsc_hwmod_class = {
.name = "adc_tsc",
.sysc = &am43xx_adc_tsc_sysc,
};
static struct omap_hwmod am43xx_adc_tsc_hwmod = {
.name = "adc_tsc",
.class = &am43xx_adc_tsc_hwmod_class,
.clkdm_name = "l3s_tsc_clkdm",
.main_clk = "adc_tsc_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* dss */
static struct omap_hwmod am43xx_dss_core_hwmod = {
@ -547,6 +578,13 @@ static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am43xx_adc_tsc_hwmod,
.clk = "dpll_core_m4_div2_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = {
.master = &am43xx_l4_hs_hwmod,
.slave = &am33xx_cpgmac0_hwmod,
@ -789,6 +827,7 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
&am43xx_l4_wkup__i2c1,
&am43xx_l4_wkup__gpio0,
&am43xx_l4_wkup__wd_timer1,
&am43xx_l4_wkup__adc_tsc,
&am43xx_l3_s__qspi,
&am33xx_l4_per__dcan0,
&am33xx_l4_per__dcan1,

25
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View File

@ -589,6 +589,7 @@ static struct omap_hwmod omap44xx_dss_hwmod = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = dss_opt_clks,
@ -647,7 +648,8 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
},
},
.dev_attr = &omap44xx_dss_dispc_dev_attr
.dev_attr = &omap44xx_dss_dispc_dev_attr,
.parent_hwmod = &omap44xx_dss_hwmod,
};
/*
@ -701,6 +703,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
},
.opt_clks = dss_dsi1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
.parent_hwmod = &omap44xx_dss_hwmod,
};
/* dss_dsi2 */
@ -733,6 +736,7 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
},
.opt_clks = dss_dsi2_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
.parent_hwmod = &omap44xx_dss_hwmod,
};
/*
@ -790,6 +794,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
},
.opt_clks = dss_hdmi_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
.parent_hwmod = &omap44xx_dss_hwmod,
};
/*
@ -819,7 +824,7 @@ static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
};
static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
{ .role = "ick", .clk = "dss_fck" },
{ .role = "ick", .clk = "l3_div_ck" },
};
static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
@ -836,6 +841,7 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
},
.opt_clks = dss_rfbi_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
.parent_hwmod = &omap44xx_dss_hwmod,
};
/*
@ -859,6 +865,7 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
},
},
.parent_hwmod = &omap44xx_dss_hwmod,
};
/*
@ -3671,7 +3678,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_dss_hwmod,
.clk = "dss_fck",
.clk = "l3_div_ck",
.addr = omap44xx_dss_dma_addrs,
.user = OCP_USER_SDMA,
};
@ -3707,7 +3714,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_dss_dispc_hwmod,
.clk = "dss_fck",
.clk = "l3_div_ck",
.addr = omap44xx_dss_dispc_dma_addrs,
.user = OCP_USER_SDMA,
};
@ -3743,7 +3750,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_dss_dsi1_hwmod,
.clk = "dss_fck",
.clk = "l3_div_ck",
.addr = omap44xx_dss_dsi1_dma_addrs,
.user = OCP_USER_SDMA,
};
@ -3779,7 +3786,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_dss_dsi2_hwmod,
.clk = "dss_fck",
.clk = "l3_div_ck",
.addr = omap44xx_dss_dsi2_dma_addrs,
.user = OCP_USER_SDMA,
};
@ -3815,7 +3822,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_dss_hdmi_hwmod,
.clk = "dss_fck",
.clk = "l3_div_ck",
.addr = omap44xx_dss_hdmi_dma_addrs,
.user = OCP_USER_SDMA,
};
@ -3851,7 +3858,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_dss_rfbi_hwmod,
.clk = "dss_fck",
.clk = "l3_div_ck",
.addr = omap44xx_dss_rfbi_dma_addrs,
.user = OCP_USER_SDMA,
};
@ -3887,7 +3894,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_dss_venc_hwmod,
.clk = "dss_fck",
.clk = "l3_div_ck",
.addr = omap44xx_dss_venc_dma_addrs,
.user = OCP_USER_SDMA,
};

5
arch/arm/mach-omap2/omap_hwmod_54xx_data.c
View File

@ -421,6 +421,7 @@ static struct omap_hwmod omap54xx_dss_dispc_hwmod = {
.opt_clks = dss_dispc_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
.dev_attr = &dss_dispc_dev_attr,
.parent_hwmod = &omap54xx_dss_hwmod,
};
/*
@ -462,6 +463,7 @@ static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = {
},
.opt_clks = dss_dsi1_a_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_dsi1_a_opt_clks),
.parent_hwmod = &omap54xx_dss_hwmod,
};
/* dss_dsi1_c */
@ -482,6 +484,7 @@ static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = {
},
.opt_clks = dss_dsi1_c_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_dsi1_c_opt_clks),
.parent_hwmod = &omap54xx_dss_hwmod,
};
/*
@ -521,6 +524,7 @@ static struct omap_hwmod omap54xx_dss_hdmi_hwmod = {
},
.opt_clks = dss_hdmi_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
.parent_hwmod = &omap54xx_dss_hwmod,
};
/*
@ -560,6 +564,7 @@ static struct omap_hwmod omap54xx_dss_rfbi_hwmod = {
},
.opt_clks = dss_rfbi_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
.parent_hwmod = &omap54xx_dss_hwmod,
};
/*

100
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
View File

@ -2075,6 +2075,70 @@ static struct omap_hwmod dra7xx_uart6_hwmod = {
},
};
/* uart7 */
static struct omap_hwmod dra7xx_uart7_hwmod = {
.name = "uart7",
.class = &dra7xx_uart_hwmod_class,
.clkdm_name = "l4per2_clkdm",
.main_clk = "uart7_gfclk_mux",
.flags = HWMOD_SWSUP_SIDLE_ACT,
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* uart8 */
static struct omap_hwmod dra7xx_uart8_hwmod = {
.name = "uart8",
.class = &dra7xx_uart_hwmod_class,
.clkdm_name = "l4per2_clkdm",
.main_clk = "uart8_gfclk_mux",
.flags = HWMOD_SWSUP_SIDLE_ACT,
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* uart9 */
static struct omap_hwmod dra7xx_uart9_hwmod = {
.name = "uart9",
.class = &dra7xx_uart_hwmod_class,
.clkdm_name = "l4per2_clkdm",
.main_clk = "uart9_gfclk_mux",
.flags = HWMOD_SWSUP_SIDLE_ACT,
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* uart10 */
static struct omap_hwmod dra7xx_uart10_hwmod = {
.name = "uart10",
.class = &dra7xx_uart_hwmod_class,
.clkdm_name = "wkupaon_clkdm",
.main_clk = "uart10_gfclk_mux",
.flags = HWMOD_SWSUP_SIDLE_ACT,
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'usb_otg_ss' class
*
@ -3095,6 +3159,38 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per2 -> uart7 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
.master = &dra7xx_l4_per2_hwmod,
.slave = &dra7xx_uart7_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per2 -> uart8 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
.master = &dra7xx_l4_per2_hwmod,
.slave = &dra7xx_uart8_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per2 -> uart9 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
.master = &dra7xx_l4_per2_hwmod,
.slave = &dra7xx_uart9_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> uart10 */
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
.master = &dra7xx_l4_wkup_hwmod,
.slave = &dra7xx_uart10_hwmod,
.clk = "wkupaon_iclk_mux",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> usb_otg_ss1 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
.master = &dra7xx_l4_per3_hwmod,
@ -3259,6 +3355,10 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_per1__uart4,
&dra7xx_l4_per1__uart5,
&dra7xx_l4_per1__uart6,
&dra7xx_l4_per2__uart7,
&dra7xx_l4_per2__uart8,
&dra7xx_l4_per2__uart9,
&dra7xx_l4_wkup__uart10,
&dra7xx_l4_per3__usb_otg_ss1,
&dra7xx_l4_per3__usb_otg_ss2,
&dra7xx_l4_per3__usb_otg_ss3,