ARM: dts: realview: DT support for the PBA8 and PBX-A9
This adds a devicetree for the ARM RealView PBA8 platform, also known as HBI-0178, "RealView Platform Baseboard for Cortex-A8" and PBX-A9 "RealView Platform Baseboard Explore for Cortex-A9" Tested in QEMU with -M realview-pb-a8, as well as with -M realview-pbx-a9 -smp cpus=2 Cc: Arnd Bergmann <arnd@arndb.de> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Tested-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
parent
2440d29d2a
commit
dfc8a11738
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@ -556,7 +556,9 @@ dtb-$(CONFIG_ARCH_REALVIEW) += \
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arm-realview-eb.dtb \
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arm-realview-eb-11mp.dtb \
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arm-realview-eb-11mp-revb.dtb \
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arm-realview-eb-a9mp.dtb
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arm-realview-eb-a9mp.dtb \
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arm-realview-pba8.dtb \
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arm-realview-pbx-a9.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += \
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rk3036-evb.dtb \
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rk3036-kylin.dtb \
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@ -0,0 +1,178 @@
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/*
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* Copyright 2016 Linaro Ltd
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
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* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/dts-v1/;
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#include "arm-realview-pbx.dtsi"
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/ {
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model = "ARM RealView Platform Baseboard for Cortex-A8";
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compatible = "arm,realview-pba8";
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arm,hbi = <0x178>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "arm,realview-smp";
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a8";
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reg = <0>;
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};
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};
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pmu: pmu@0 {
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compatible = "arm,cortex-a8-pmu";
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interrupt-parent = <&intc>;
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interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>;
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};
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/* Primary GIC PL390 interrupt controller in the test chip */
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intc: interrupt-controller@1e000000 {
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compatible = "arm,pl390";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0x1e001000 0x1000>,
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<0x1e000000 0x100>;
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};
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};
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ðernet {
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interrupt-parent = <&intc>;
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interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
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};
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&usb {
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interrupt-parent = <&intc>;
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interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
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};
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&soc {
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compatible = "arm,realview-pba8-soc", "simple-bus";
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};
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&syscon {
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compatible = "arm,realview-pba8-syscon", "syscon", "simple-mfd";
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};
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&serial0 {
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interrupt-parent = <&intc>;
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interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
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};
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&serial1 {
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interrupt-parent = <&intc>;
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interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
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};
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&serial2 {
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interrupt-parent = <&intc>;
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interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
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};
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&serial3 {
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interrupt-parent = <&intc>;
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interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
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};
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&ssp {
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interrupt-parent = <&intc>;
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interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
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};
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&wdog0 {
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interrupt-parent = <&intc>;
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interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
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};
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&wdog1 {
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interrupt-parent = <&intc>;
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interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
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};
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&timer01 {
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interrupt-parent = <&intc>;
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interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
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};
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&timer23 {
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interrupt-parent = <&intc>;
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interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
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};
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&gpio0 {
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interrupt-parent = <&intc>;
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interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
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};
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&gpio1 {
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interrupt-parent = <&intc>;
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interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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&gpio2 {
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interrupt-parent = <&intc>;
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interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
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};
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&rtc {
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interrupt-parent = <&intc>;
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interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
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};
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&timer45 {
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interrupt-parent = <&intc>;
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interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
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};
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&timer67 {
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interrupt-parent = <&intc>;
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interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
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};
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&aaci {
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interrupt-parent = <&intc>;
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interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
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};
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&mmc {
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interrupt-parent = <&intc>;
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interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
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<0 18 IRQ_TYPE_LEVEL_HIGH>;
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};
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&kmi0 {
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interrupt-parent = <&intc>;
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interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
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};
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&kmi1 {
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interrupt-parent = <&intc>;
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interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
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};
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&clcd {
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interrupt-parent = <&intc>;
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interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
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};
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@ -0,0 +1,229 @@
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/*
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* Copyright 2016 Linaro Ltd
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
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* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/dts-v1/;
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#include "arm-realview-pbx.dtsi"
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/ {
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/*
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* This is the RealView Platform Baseboard Explore for Cortex-A9
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* (HBI0182 + HBI0183) as described in ARM DUI 0440B
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*/
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model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
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arm,hbi = <0x182>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "arm,realview-smp";
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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};
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};
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0x0>;
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next-level-cache = <&L2>;
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0x1>;
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next-level-cache = <&L2>;
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};
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};
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L2: l2-cache {
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compatible = "arm,pl310-cache";
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reg = <0x1f002000 0x1000>;
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cache-unified;
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cache-level = <2>;
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/*
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* Override default cache size, sets and
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* associativity as these may be erroneously set
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* up by boot loader(s).
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*/
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cache-size = <1048576>; // 1MB
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cache-sets = <4096>;
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cache-line-size = <32>;
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arm,parity-disable;
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arm,tag-latency = <1>;
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arm,data-latency = <1 1>;
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arm,dirty-latency = <1>;
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};
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scu: scu@1f000000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0x1f000000 0x100>;
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};
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twd_timer: timer@1f000600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x1f000600 0x20>;
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interrupt-parent = <&intc>;
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interrupts = <1 13 0xf04>;
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};
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twd_wdog: watchdog@1f000620 {
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compatible = "arm,cortex-a9-twd-wdt";
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reg = <0x1f000620 0x20>;
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interrupt-parent = <&intc>;
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interrupts = <1 14 0xf04>;
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};
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pmu: pmu@0 {
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compatible = "arm,cortex-a9-pmu";
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interrupt-parent = <&intc>;
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interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>,
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<0 45 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&CPU0>, <&CPU1>;
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};
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/* Primary GIC PL390 interrupt controller in the test chip */
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intc: interrupt-controller@1f000000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0x1f001000 0x1000>,
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<0x1f000100 0x100>;
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};
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};
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ðernet {
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interrupt-parent = <&intc>;
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interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
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};
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&usb {
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interrupt-parent = <&intc>;
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interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
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};
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&serial0 {
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interrupt-parent = <&intc>;
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interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
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};
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&serial1 {
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interrupt-parent = <&intc>;
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interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
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};
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&serial2 {
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interrupt-parent = <&intc>;
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interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
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};
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&serial3 {
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interrupt-parent = <&intc>;
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interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
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};
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&ssp {
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interrupt-parent = <&intc>;
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interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
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};
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&wdog0 {
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interrupt-parent = <&intc>;
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interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
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};
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&wdog1 {
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interrupt-parent = <&intc>;
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interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
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};
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&timer01 {
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interrupt-parent = <&intc>;
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interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
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};
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&timer23 {
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interrupt-parent = <&intc>;
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interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
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};
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&gpio0 {
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interrupt-parent = <&intc>;
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interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
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};
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&gpio1 {
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interrupt-parent = <&intc>;
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interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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&gpio2 {
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interrupt-parent = <&intc>;
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interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
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};
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&rtc {
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interrupt-parent = <&intc>;
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interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
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};
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&timer45 {
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interrupt-parent = <&intc>;
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interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
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};
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&timer67 {
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interrupt-parent = <&intc>;
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interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
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};
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&aaci {
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interrupt-parent = <&intc>;
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interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
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};
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&mmc {
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interrupt-parent = <&intc>;
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interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
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<0 18 IRQ_TYPE_LEVEL_HIGH>;
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};
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&kmi0 {
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interrupt-parent = <&intc>;
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interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
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};
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&kmi1 {
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interrupt-parent = <&intc>;
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interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
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};
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&clcd {
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interrupt-parent = <&intc>;
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interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
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};
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@ -0,0 +1,542 @@
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/*
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* Copyright 2016 Linaro Ltd
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "arm,realview-pbx";
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chosen { };
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aliases {
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serial0 = &serial0;
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serial1 = &serial1;
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serial2 = &serial2;
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serial3 = &serial3;
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i2c0 = &i2c;
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};
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memory {
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/* 128 MiB memory @ 0x0 */
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reg = <0x00000000 0x08000000>;
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};
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/* The voltage to the MMC card is hardwired at 3.3V */
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vmmc: fixedregulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "vmmc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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veth: fixedregulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "veth";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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xtal24mhz: xtal24mhz@24M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
|
||||
};
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||||
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refclk32khz: refclk32khz {
|
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
|
||||
};
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||||
timclk: timclk@1M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <24>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
|
||||
mclk: mclk@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
|
||||
kmiclk: kmiclk@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
|
||||
sspclk: sspclk@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
|
||||
uartclk: uartclk@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
|
||||
wdogclk: wdogclk@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
|
||||
/* FIXME: this actually hangs off the PLL clocks */
|
||||
pclk: pclk@0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
flash0@40000000 {
|
||||
/* 2 * 32MiB NOR Flash memory */
|
||||
compatible = "arm,versatile-flash", "cfi-flash";
|
||||
reg = <0x40000000 0x04000000>;
|
||||
bank-width = <4>;
|
||||
};
|
||||
|
||||
flash1@44000000 {
|
||||
/* 2 * 32MiB NOR Flash memory */
|
||||
compatible = "arm,versatile-flash", "cfi-flash";
|
||||
reg = <0x44000000 0x04000000>;
|
||||
bank-width = <4>;
|
||||
};
|
||||
|
||||
/* SMSC 9118 ethernet with PHY and EEPROM */
|
||||
ethernet: ethernet@4e000000 {
|
||||
compatible = "smsc,lan9118", "smsc,lan9115";
|
||||
reg = <0x4e000000 0x10000>;
|
||||
phy-mode = "mii";
|
||||
reg-io-width = <4>;
|
||||
smsc,irq-active-high;
|
||||
smsc,irq-push-pull;
|
||||
vdd33a-supply = <&veth>;
|
||||
vddvario-supply = <&veth>;
|
||||
};
|
||||
|
||||
usb: usb@4f000000 {
|
||||
compatible = "nxp,usb-isp1761";
|
||||
reg = <0x4f000000 0x20000>;
|
||||
port1-otg;
|
||||
};
|
||||
|
||||
soc: soc@0 {
|
||||
compatible = "arm,realview-pbx-soc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
regmap = <&syscon>;
|
||||
ranges;
|
||||
|
||||
syscon: syscon@10000000 {
|
||||
compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd";
|
||||
reg = <0x10000000 0x1000>;
|
||||
|
||||
led@08.0 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x01>;
|
||||
label = "versatile:0";
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "on";
|
||||
};
|
||||
led@08.1 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x02>;
|
||||
label = "versatile:1";
|
||||
linux,default-trigger = "mmc0";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.2 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x04>;
|
||||
label = "versatile:2";
|
||||
linux,default-trigger = "cpu0";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.3 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x08>;
|
||||
label = "versatile:3";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.4 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x10>;
|
||||
label = "versatile:4";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.5 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x20>;
|
||||
label = "versatile:5";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.6 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x40>;
|
||||
label = "versatile:6";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.7 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x80>;
|
||||
label = "versatile:7";
|
||||
default-state = "off";
|
||||
};
|
||||
oscclk0: osc0@0c {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x0C>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
oscclk1: osc1@10 {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x10>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
oscclk2: osc2@14 {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x14>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
oscclk3: osc3@18 {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x18>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
oscclk4: osc4@1c {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x1c>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
};
|
||||
|
||||
sp810_syscon0: sysctl@10001000 {
|
||||
compatible = "arm,sp810", "arm,primecell";
|
||||
reg = <0x10001000 0x1000>;
|
||||
clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
|
||||
clock-names = "refclk", "timclk", "apb_pclk";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "timerclk0",
|
||||
"timerclk1",
|
||||
"timerclk2",
|
||||
"timerclk3";
|
||||
assigned-clocks = <&sp810_syscon0 0>,
|
||||
<&sp810_syscon0 1>,
|
||||
<&sp810_syscon0 2>,
|
||||
<&sp810_syscon0 3>;
|
||||
assigned-clock-parents = <&timclk>,
|
||||
<&timclk>,
|
||||
<&timclk>,
|
||||
<&timclk>;
|
||||
};
|
||||
|
||||
i2c: i2c@10002000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "arm,versatile-i2c";
|
||||
reg = <0x10002000 0x1000>;
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1338";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@10009000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x10009000 0x1000>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
serial1: serial@1000a000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
serial2: serial@1000b000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x1000b000 0x1000>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
ssp: ssp@1000d000 {
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0x1000d000 0x1000>;
|
||||
clocks = <&sspclk>, <&pclk>;
|
||||
clock-names = "SSPCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
wdog0: watchdog@1000f000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x1000f000 0x1000>;
|
||||
clocks = <&wdogclk>, <&pclk>;
|
||||
clock-names = "wdogclk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog1: watchdog@10010000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x10010000 0x1000>;
|
||||
clocks = <&wdogclk>, <&pclk>;
|
||||
clock-names = "wdogclk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer01: timer@10011000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x10011000 0x1000>;
|
||||
clocks = <&sp810_syscon0 0>,
|
||||
<&sp810_syscon0 1>,
|
||||
<&pclk>;
|
||||
clock-names = "timerclk0",
|
||||
"timerclk1",
|
||||
"apb_pclk";
|
||||
};
|
||||
|
||||
timer23: timer@10012000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x10012000 0x1000>;
|
||||
clocks = <&sp810_syscon0 2>,
|
||||
<&sp810_syscon0 3>,
|
||||
<&pclk>;
|
||||
clock-names = "timerclk2",
|
||||
"timerclk3",
|
||||
"apb_pclk";
|
||||
};
|
||||
|
||||
gpio0: gpio@10013000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x10013000 0x1000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
gpio1: gpio@10014000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x10014000 0x1000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
gpio2: gpio@10015000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x10015000 0x1000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
/* DVI serial bus control is at 10016000 */
|
||||
|
||||
rtc: rtc@10017000 {
|
||||
compatible = "arm,pl031", "arm,primecell";
|
||||
reg = <0x10017000 0x1000>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
timer45: timer@10018000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x10018000 0x1000>;
|
||||
clocks = <&timclk>, <&timclk>, <&pclk>;
|
||||
clock-names = "timerclk4", "timerclk5", "apb_pclk";
|
||||
};
|
||||
|
||||
timer67: timer@10019000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x10019000 0x1000>;
|
||||
clocks = <&timclk>, <&timclk>, <&pclk>;
|
||||
clock-names = "timerclk6", "timerclk7", "apb_pclk";
|
||||
};
|
||||
|
||||
sp810_syscon1: sysctl@1001a000 {
|
||||
compatible = "arm,sp810", "arm,primecell";
|
||||
reg = <0x1001a000 0x1000>;
|
||||
clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
|
||||
clock-names = "refclk", "timclk", "apb_pclk";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "timerclk4",
|
||||
"timerclk5",
|
||||
"timerclk6",
|
||||
"timerclk7";
|
||||
assigned-clocks = <&sp810_syscon1 0>,
|
||||
<&sp810_syscon1 1>,
|
||||
<&sp810_syscon1 2>,
|
||||
<&sp810_syscon1 3>;
|
||||
assigned-clock-parents = <&timclk>,
|
||||
<&timclk>,
|
||||
<&timclk>,
|
||||
<&timclk>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
/* These peripherals are inside the FPGA */
|
||||
fpga {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
aaci: aaci@10004000 {
|
||||
compatible = "arm,pl041", "arm,primecell";
|
||||
reg = <0x10004000 0x1000>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
mmc: mmcsd@10005000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
reg = <0x10005000 0x1000>;
|
||||
|
||||
/* Due to frequent FIFO overruns, use just 500 kHz */
|
||||
max-frequency = <500000>;
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
clocks = <&mclk>, <&pclk>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
vmmc-supply = <&vmmc>;
|
||||
cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
kmi0: kmi@10006000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x10006000 0x1000>;
|
||||
clocks = <&kmiclk>, <&pclk>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
kmi1: kmi@10007000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x10007000 0x1000>;
|
||||
clocks = <&kmiclk>, <&pclk>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
serial3: serial@1000c000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x1000c000 0x1000>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
};
|
||||
|
||||
/* These peripherals are inside the NEC ISSP */
|
||||
issp {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
clcd: clcd@10020000 {
|
||||
compatible = "arm,pl111", "arm,primecell";
|
||||
reg = <0x10020000 0x1000>;
|
||||
interrupt-names = "combined";
|
||||
clocks = <&oscclk4>, <&pclk>;
|
||||
clock-names = "clcdclk", "apb_pclk";
|
||||
|
||||
port {
|
||||
clcd_pads: endpoint {
|
||||
remote-endpoint = <&clcd_panel>;
|
||||
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
|
||||
};
|
||||
};
|
||||
|
||||
panel {
|
||||
compatible = "panel-dpi";
|
||||
|
||||
port {
|
||||
clcd_panel: endpoint {
|
||||
remote-endpoint = <&clcd_pads>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Standard 640x480 VGA timings */
|
||||
panel-timing {
|
||||
clock-frequency = <25175000>;
|
||||
hactive = <640>;
|
||||
hback-porch = <48>;
|
||||
hfront-porch = <16>;
|
||||
hsync-len = <96>;
|
||||
vactive = <480>;
|
||||
vback-porch = <33>;
|
||||
vfront-porch = <10>;
|
||||
vsync-len = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue