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drm/amd/powerplay: parameter updates according to SMC. 

Update to latest changes for SMC team.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2016-03-23 15:04:23 +08:00 committed by Alex Deucher
parent 9e26bbb36a
commit e16ff21d2a
2 changed files with 22 additions and 20 deletions
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32
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c
View File

@ -57,6 +57,13 @@ void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
}
static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
{
uint32_t tmp;
tmp = raw_setting * 4096 / 100;
return (uint16_t)tmp;
}
int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
{
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
@ -65,6 +72,8 @@ int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
struct pp_advance_fan_control_parameters *fan_table=
&hwmgr->thermal_controller.advanceFanControlParameters;
int i, j, k;
uint16_t *pdef1;
uint16_t *pdef2;
@ -75,15 +84,16 @@ int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
"Target Operating Temp is out of Range!",
);
/* This is the same value as TemperatureLimitHigh except it is integer with no fraction bit. */
dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp);
/* HW request to hard code this value to 8 which is 0.5C */
dpm_table->GpuTjHyst = 8;
dpm_table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
cac_dtp_table->usTargetOperatingTemp * 256);
dpm_table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
cac_dtp_table->usTemperatureLimitHotspot * 256);
dpm_table->FanGainEdge = PP_HOST_TO_SMC_US(
scale_fan_gain_settings(fan_table->usFanGainEdge));
dpm_table->FanGainHotspot = PP_HOST_TO_SMC_US(
scale_fan_gain_settings(fan_table->usFanGainHotspot));
dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase;
dpm_table->DTETjOffset = (uint8_t)(data->dte_tj_offset);
dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->BAPM_TEMP_GRADIENT);
pdef1 = defaults->BAPMTI_R;
pdef2 = defaults->BAPMTI_RC;
@ -330,14 +340,6 @@ int polaris10_enable_power_containment(struct pp_hwmgr *hwmgr)
data->power_containment_features = 0;
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PowerContainment)) {
if (data->enable_dte_feature) {
smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
(uint16_t)(PPSMC_MSG_EnableDTE));
PP_ASSERT_WITH_CODE((0 == smc_result),
"Failed to enable DTE in SMC.", result = -1;);
if (0 == smc_result)
data->power_containment_features |= POWERCONTAINMENT_FEATURE_DTE;
}
if (data->enable_tdc_limit_feature) {
smc_result = smum_send_msg_to_smc(hwmgr->smumgr,

10
drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
View File

@ -323,14 +323,14 @@ struct SMU74_Discrete_DpmTable {
uint16_t BAPMTI_R[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
uint16_t BAPMTI_RC[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
uint8_t DTEAmbientTempBase;
uint8_t DTETjOffset;
uint8_t GpuTjMax;
uint8_t GpuTjHyst;
uint16_t TemperatureLimitEdge;
uint16_t TemperatureLimitHotspot;
uint16_t BootVddc;
uint16_t BootVddci;
uint32_t BAPM_TEMP_GRADIENT;
uint16_t FanGainEdge;
uint16_t FanGainHotspot;
uint32_t LowSclkInterruptThreshold;
uint32_t VddGfxReChkWait;