spi: at91-usart: Add driver for at91-usart as SPI
This is the driver for at91-usart in spi mode. The USART IP can be configured to work in many modes and one of them is SPI. The driver was tested on sama5d3-xplained and sama5d4-xplained boards with enc28j60 ethernet controller as slave. Signed-off-by: Radu Pirea <radu.pirea@microchip.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviwed-by: Mark Brown <broonie@kernel.org> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Radu Pirea
Lee Jones
parent
937c0a26ac
commit
e1892546ff
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@ -83,6 +83,14 @@ config SPI_ATMEL
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This selects a driver for the Atmel SPI Controller, present on
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many AT91 ARM chips.
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config SPI_AT91_USART
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tristate "Atmel USART Controller SPI driver"
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depends on (ARCH_AT91 || COMPILE_TEST)
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depends on MFD_AT91_USART
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help
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This selects a driver for the AT91 USART Controller as SPI Master,
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present on AT91 and SAMA5 SoC series.
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config SPI_AU1550
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tristate "Au1550/Au1200/Au1300 SPI Controller"
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depends on MIPS_ALCHEMY
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@ -16,6 +16,7 @@ obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
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obj-$(CONFIG_SPI_ALTERA) += spi-altera.o
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obj-$(CONFIG_SPI_ARMADA_3700) += spi-armada-3700.o
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obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
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obj-$(CONFIG_SPI_AT91_USART) += spi-at91-usart.o
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obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
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obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
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obj-$(CONFIG_SPI_AXI_SPI_ENGINE) += spi-axi-spi-engine.o
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@ -0,0 +1,432 @@
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// SPDX-License-Identifier: GPL-2.0
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//
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// Driver for AT91 USART Controllers as SPI
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//
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// Copyright (C) 2018 Microchip Technology Inc.
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//
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// Author: Radu Pirea <radu.pirea@microchip.com>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_gpio.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#define US_CR 0x00
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#define US_MR 0x04
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#define US_IER 0x08
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#define US_IDR 0x0C
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#define US_CSR 0x14
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#define US_RHR 0x18
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#define US_THR 0x1C
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#define US_BRGR 0x20
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#define US_VERSION 0xFC
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#define US_CR_RSTRX BIT(2)
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#define US_CR_RSTTX BIT(3)
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#define US_CR_RXEN BIT(4)
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#define US_CR_RXDIS BIT(5)
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#define US_CR_TXEN BIT(6)
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#define US_CR_TXDIS BIT(7)
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#define US_MR_SPI_MASTER 0x0E
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#define US_MR_CHRL GENMASK(7, 6)
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#define US_MR_CPHA BIT(8)
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#define US_MR_CPOL BIT(16)
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#define US_MR_CLKO BIT(18)
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#define US_MR_WRDBT BIT(20)
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#define US_MR_LOOP BIT(15)
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#define US_IR_RXRDY BIT(0)
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#define US_IR_TXRDY BIT(1)
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#define US_IR_OVRE BIT(5)
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#define US_BRGR_SIZE BIT(16)
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#define US_MIN_CLK_DIV 0x06
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#define US_MAX_CLK_DIV BIT(16)
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#define US_RESET (US_CR_RSTRX | US_CR_RSTTX)
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#define US_DISABLE (US_CR_RXDIS | US_CR_TXDIS)
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#define US_ENABLE (US_CR_RXEN | US_CR_TXEN)
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#define US_OVRE_RXRDY_IRQS (US_IR_OVRE | US_IR_RXRDY)
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#define US_INIT \
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(US_MR_SPI_MASTER | US_MR_CHRL | US_MR_CLKO | US_MR_WRDBT)
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/* Register access macros */
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#define at91_usart_spi_readl(port, reg) \
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readl_relaxed((port)->regs + US_##reg)
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#define at91_usart_spi_writel(port, reg, value) \
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writel_relaxed((value), (port)->regs + US_##reg)
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#define at91_usart_spi_readb(port, reg) \
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readb_relaxed((port)->regs + US_##reg)
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#define at91_usart_spi_writeb(port, reg, value) \
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writeb_relaxed((value), (port)->regs + US_##reg)
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struct at91_usart_spi {
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struct spi_transfer *current_transfer;
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void __iomem *regs;
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struct device *dev;
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struct clk *clk;
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/*used in interrupt to protect data reading*/
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spinlock_t lock;
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int irq;
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unsigned int current_tx_remaining_bytes;
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unsigned int current_rx_remaining_bytes;
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u32 spi_clk;
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u32 status;
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bool xfer_failed;
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};
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static inline u32 at91_usart_spi_tx_ready(struct at91_usart_spi *aus)
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{
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return aus->status & US_IR_TXRDY;
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}
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static inline u32 at91_usart_spi_rx_ready(struct at91_usart_spi *aus)
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{
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return aus->status & US_IR_RXRDY;
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}
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static inline u32 at91_usart_spi_check_overrun(struct at91_usart_spi *aus)
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{
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return aus->status & US_IR_OVRE;
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}
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static inline u32 at91_usart_spi_read_status(struct at91_usart_spi *aus)
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{
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aus->status = at91_usart_spi_readl(aus, CSR);
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return aus->status;
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}
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static inline void at91_usart_spi_tx(struct at91_usart_spi *aus)
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{
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unsigned int len = aus->current_transfer->len;
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unsigned int remaining = aus->current_tx_remaining_bytes;
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const u8 *tx_buf = aus->current_transfer->tx_buf;
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if (!remaining)
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return;
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if (at91_usart_spi_tx_ready(aus)) {
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at91_usart_spi_writeb(aus, THR, tx_buf[len - remaining]);
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aus->current_tx_remaining_bytes--;
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}
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}
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static inline void at91_usart_spi_rx(struct at91_usart_spi *aus)
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{
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int len = aus->current_transfer->len;
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int remaining = aus->current_rx_remaining_bytes;
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u8 *rx_buf = aus->current_transfer->rx_buf;
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if (!remaining)
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return;
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rx_buf[len - remaining] = at91_usart_spi_readb(aus, RHR);
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aus->current_rx_remaining_bytes--;
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}
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static inline void
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at91_usart_spi_set_xfer_speed(struct at91_usart_spi *aus,
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struct spi_transfer *xfer)
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{
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at91_usart_spi_writel(aus, BRGR,
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DIV_ROUND_UP(aus->spi_clk, xfer->speed_hz));
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}
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static irqreturn_t at91_usart_spi_interrupt(int irq, void *dev_id)
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{
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struct spi_controller *controller = dev_id;
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struct at91_usart_spi *aus = spi_master_get_devdata(controller);
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spin_lock(&aus->lock);
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at91_usart_spi_read_status(aus);
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if (at91_usart_spi_check_overrun(aus)) {
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aus->xfer_failed = true;
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at91_usart_spi_writel(aus, IDR, US_IR_OVRE | US_IR_RXRDY);
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spin_unlock(&aus->lock);
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return IRQ_HANDLED;
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}
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if (at91_usart_spi_rx_ready(aus)) {
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at91_usart_spi_rx(aus);
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spin_unlock(&aus->lock);
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return IRQ_HANDLED;
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}
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spin_unlock(&aus->lock);
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return IRQ_NONE;
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}
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static int at91_usart_spi_setup(struct spi_device *spi)
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{
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struct at91_usart_spi *aus = spi_master_get_devdata(spi->controller);
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u32 *ausd = spi->controller_state;
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unsigned int mr = at91_usart_spi_readl(aus, MR);
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u8 bits = spi->bits_per_word;
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if (bits != 8) {
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dev_dbg(&spi->dev, "Only 8 bits per word are supported\n");
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return -EINVAL;
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}
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if (spi->mode & SPI_CPOL)
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mr |= US_MR_CPOL;
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else
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mr &= ~US_MR_CPOL;
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if (spi->mode & SPI_CPHA)
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mr |= US_MR_CPHA;
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else
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mr &= ~US_MR_CPHA;
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if (spi->mode & SPI_LOOP)
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mr |= US_MR_LOOP;
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else
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mr &= ~US_MR_LOOP;
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if (!ausd) {
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ausd = kzalloc(sizeof(*ausd), GFP_KERNEL);
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if (!ausd)
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return -ENOMEM;
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spi->controller_state = ausd;
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}
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*ausd = mr;
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dev_dbg(&spi->dev,
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"setup: bpw %u mode 0x%x -> mr %d %08x\n",
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bits, spi->mode, spi->chip_select, mr);
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return 0;
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}
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int at91_usart_spi_transfer_one(struct spi_controller *ctlr,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
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at91_usart_spi_set_xfer_speed(aus, xfer);
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aus->xfer_failed = false;
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aus->current_transfer = xfer;
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aus->current_tx_remaining_bytes = xfer->len;
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aus->current_rx_remaining_bytes = xfer->len;
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while ((aus->current_tx_remaining_bytes ||
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aus->current_rx_remaining_bytes) && !aus->xfer_failed) {
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at91_usart_spi_read_status(aus);
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at91_usart_spi_tx(aus);
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cpu_relax();
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}
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if (aus->xfer_failed) {
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dev_err(aus->dev, "Overrun!\n");
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return -EIO;
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}
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return 0;
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}
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int at91_usart_spi_prepare_message(struct spi_controller *ctlr,
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struct spi_message *message)
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{
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struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
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struct spi_device *spi = message->spi;
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u32 *ausd = spi->controller_state;
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at91_usart_spi_writel(aus, CR, US_ENABLE);
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at91_usart_spi_writel(aus, IER, US_OVRE_RXRDY_IRQS);
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at91_usart_spi_writel(aus, MR, *ausd);
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return 0;
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}
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int at91_usart_spi_unprepare_message(struct spi_controller *ctlr,
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struct spi_message *message)
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{
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struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
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at91_usart_spi_writel(aus, CR, US_RESET | US_DISABLE);
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at91_usart_spi_writel(aus, IDR, US_OVRE_RXRDY_IRQS);
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return 0;
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}
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static void at91_usart_spi_cleanup(struct spi_device *spi)
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{
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struct at91_usart_spi_device *ausd = spi->controller_state;
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spi->controller_state = NULL;
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kfree(ausd);
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}
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static void at91_usart_spi_init(struct at91_usart_spi *aus)
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{
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at91_usart_spi_writel(aus, MR, US_INIT);
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at91_usart_spi_writel(aus, CR, US_RESET | US_DISABLE);
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}
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static int at91_usart_gpio_setup(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.parent->of_node;
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int i;
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int ret;
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int nb;
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if (!np)
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return -EINVAL;
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nb = of_gpio_named_count(np, "cs-gpios");
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for (i = 0; i < nb; i++) {
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int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
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if (cs_gpio < 0)
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return cs_gpio;
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if (gpio_is_valid(cs_gpio)) {
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ret = devm_gpio_request_one(&pdev->dev, cs_gpio,
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GPIOF_DIR_OUT,
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dev_name(&pdev->dev));
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if (ret)
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return ret;
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}
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}
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return 0;
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}
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static int at91_usart_spi_probe(struct platform_device *pdev)
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{
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struct resource *regs;
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struct spi_controller *controller;
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struct at91_usart_spi *aus;
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struct clk *clk;
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int irq;
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int ret;
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regs = platform_get_resource(to_platform_device(pdev->dev.parent),
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IORESOURCE_MEM, 0);
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if (!regs)
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return -EINVAL;
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irq = platform_get_irq(to_platform_device(pdev->dev.parent), 0);
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if (irq < 0)
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return irq;
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clk = devm_clk_get(pdev->dev.parent, "usart");
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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ret = -ENOMEM;
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controller = spi_alloc_master(&pdev->dev, sizeof(*aus));
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if (!controller)
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goto at91_usart_spi_probe_fail;
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ret = at91_usart_gpio_setup(pdev);
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if (ret)
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goto at91_usart_spi_probe_fail;
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controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH;
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controller->dev.of_node = pdev->dev.parent->of_node;
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controller->bits_per_word_mask = SPI_BPW_MASK(8);
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controller->setup = at91_usart_spi_setup;
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controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
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controller->transfer_one = at91_usart_spi_transfer_one;
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controller->prepare_message = at91_usart_spi_prepare_message;
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controller->unprepare_message = at91_usart_spi_unprepare_message;
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controller->cleanup = at91_usart_spi_cleanup;
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controller->max_speed_hz = DIV_ROUND_UP(clk_get_rate(clk),
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US_MIN_CLK_DIV);
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controller->min_speed_hz = DIV_ROUND_UP(clk_get_rate(clk),
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US_MAX_CLK_DIV);
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platform_set_drvdata(pdev, controller);
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aus = spi_master_get_devdata(controller);
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aus->dev = &pdev->dev;
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aus->regs = devm_ioremap_resource(&pdev->dev, regs);
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if (IS_ERR(aus->regs)) {
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ret = PTR_ERR(aus->regs);
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goto at91_usart_spi_probe_fail;
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}
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aus->irq = irq;
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aus->clk = clk;
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ret = devm_request_irq(&pdev->dev, irq, at91_usart_spi_interrupt, 0,
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dev_name(&pdev->dev), controller);
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if (ret)
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goto at91_usart_spi_probe_fail;
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ret = clk_prepare_enable(clk);
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if (ret)
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goto at91_usart_spi_probe_fail;
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aus->spi_clk = clk_get_rate(clk);
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at91_usart_spi_init(aus);
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spin_lock_init(&aus->lock);
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ret = devm_spi_register_master(&pdev->dev, controller);
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if (ret)
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goto at91_usart_fail_register_master;
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dev_info(&pdev->dev,
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"AT91 USART SPI Controller version 0x%x at %pa (irq %d)\n",
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at91_usart_spi_readl(aus, VERSION),
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®s->start, irq);
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return 0;
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at91_usart_fail_register_master:
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clk_disable_unprepare(clk);
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at91_usart_spi_probe_fail:
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spi_master_put(controller);
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return ret;
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}
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static int at91_usart_spi_remove(struct platform_device *pdev)
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{
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struct spi_controller *ctlr = platform_get_drvdata(pdev);
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struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
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clk_disable_unprepare(aus->clk);
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return 0;
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}
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static const struct of_device_id at91_usart_spi_dt_ids[] = {
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{ .compatible = "microchip,at91sam9g45-usart-spi"},
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{ /* sentinel */}
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};
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MODULE_DEVICE_TABLE(of, at91_usart_spi_dt_ids);
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static struct platform_driver at91_usart_spi_driver = {
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.driver = {
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.name = "at91_usart_spi",
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},
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.probe = at91_usart_spi_probe,
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.remove = at91_usart_spi_remove,
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};
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|
||||
module_platform_driver(at91_usart_spi_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Microchip AT91 USART SPI Controller driver");
|
||||
MODULE_AUTHOR("Radu Pirea <radu.pirea@microchip.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:at91_usart_spi");
|
||||
Loading…
Reference in New Issue