drm/nouveau/kms/nv50: remove code to support non-atomic page flips
Made completely unreachable (and broken) by atomic commits. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
c2d926aacc
commit
e1ef6b42d9
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@ -835,10 +835,7 @@ nouveau_page_flip_emit(struct nouveau_channel *chan,
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if (ret)
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goto fail;
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if (drm->device.info.family < NV_DEVICE_INFO_V0_FERMI)
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BEGIN_NV04(chan, NvSubSw, NV_SW_PAGE_FLIP, 1);
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else
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BEGIN_NVC0(chan, FermiSw, NV_SW_PAGE_FLIP, 1);
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BEGIN_NV04(chan, NvSubSw, NV_SW_PAGE_FLIP, 1);
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OUT_RING (chan, 0x00000000);
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FIRE_RING (chan);
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@ -867,6 +864,8 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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struct nouveau_channel *chan;
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struct nouveau_cli *cli;
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struct nouveau_fence *fence;
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struct nv04_display *dispnv04 = nv04_display(dev);
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int head = nouveau_crtc(crtc)->index;
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int ret;
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chan = drm->channel;
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@ -913,32 +912,23 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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drm_crtc_vblank_get(crtc);
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/* Emit a page flip */
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if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
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ret = nv50_display_flip_next(crtc, fb, chan, swap_interval);
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if (swap_interval) {
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ret = RING_SPACE(chan, 8);
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if (ret)
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goto fail_unreserve;
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} else {
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struct nv04_display *dispnv04 = nv04_display(dev);
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int head = nouveau_crtc(crtc)->index;
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if (swap_interval) {
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ret = RING_SPACE(chan, 8);
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if (ret)
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goto fail_unreserve;
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BEGIN_NV04(chan, NvSubImageBlit, 0x012c, 1);
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OUT_RING (chan, 0);
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BEGIN_NV04(chan, NvSubImageBlit, 0x0134, 1);
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OUT_RING (chan, head);
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BEGIN_NV04(chan, NvSubImageBlit, 0x0100, 1);
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OUT_RING (chan, 0);
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BEGIN_NV04(chan, NvSubImageBlit, 0x0130, 1);
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OUT_RING (chan, 0);
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}
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nouveau_bo_ref(new_bo, &dispnv04->image[head]);
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BEGIN_NV04(chan, NvSubImageBlit, 0x012c, 1);
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OUT_RING (chan, 0);
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BEGIN_NV04(chan, NvSubImageBlit, 0x0134, 1);
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OUT_RING (chan, head);
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BEGIN_NV04(chan, NvSubImageBlit, 0x0100, 1);
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OUT_RING (chan, 0);
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BEGIN_NV04(chan, NvSubImageBlit, 0x0130, 1);
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OUT_RING (chan, 0);
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}
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nouveau_bo_ref(new_bo, &dispnv04->image[head]);
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ret = nouveau_page_flip_emit(chan, old_bo, new_bo, s, &fence);
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if (ret)
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goto fail_unreserve;
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@ -986,16 +976,8 @@ nouveau_finish_page_flip(struct nouveau_channel *chan,
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s = list_first_entry(&fctx->flip, struct nouveau_page_flip_state, head);
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if (s->event) {
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if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) {
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drm_crtc_arm_vblank_event(s->crtc, s->event);
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} else {
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drm_crtc_send_vblank_event(s->crtc, s->event);
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/* Give up ownership of vblank for page-flipped crtc */
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drm_crtc_vblank_put(s->crtc);
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}
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}
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else {
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drm_crtc_arm_vblank_event(s->crtc, s->event);
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} else {
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/* Give up ownership of vblank for page-flipped crtc */
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drm_crtc_vblank_put(s->crtc);
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}
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@ -1017,12 +999,10 @@ nouveau_flip_complete(struct nvif_notify *notify)
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struct nouveau_page_flip_state state;
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if (!nouveau_finish_page_flip(chan, &state)) {
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if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) {
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nv_set_crtc_base(drm->dev, drm_crtc_index(state.crtc),
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state.offset + state.crtc->y *
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state.pitch + state.crtc->x *
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state.bpp / 8);
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}
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nv_set_crtc_base(drm->dev, drm_crtc_index(state.crtc),
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state.offset + state.crtc->y *
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state.pitch + state.crtc->x *
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state.bpp / 8);
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}
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return NVIF_NOTIFY_KEEP;
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@ -92,7 +92,6 @@ struct nv84_fence_chan {
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struct nouveau_fence_chan base;
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struct nvkm_vma vma;
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struct nvkm_vma vma_gart;
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struct nvkm_vma dispc_vma[4];
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};
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struct nv84_fence_priv {
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@ -102,7 +101,6 @@ struct nv84_fence_priv {
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u32 *suspend;
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};
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u64 nv84_fence_crtc(struct nouveau_channel *, int);
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int nv84_fence_context_new(struct nouveau_channel *);
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#endif
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@ -57,10 +57,7 @@ void
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nv10_fence_context_del(struct nouveau_channel *chan)
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{
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struct nv10_fence_chan *fctx = chan->fence;
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int i;
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nouveau_fence_context_del(&fctx->base);
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for (i = 0; i < ARRAY_SIZE(fctx->head); i++)
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nvif_object_fini(&fctx->head[i]);
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nvif_object_fini(&fctx->sema);
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chan->fence = NULL;
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nouveau_fence_context_free(&fctx->base);
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@ -7,7 +7,6 @@
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struct nv10_fence_chan {
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struct nouveau_fence_chan base;
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struct nvif_object sema;
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struct nvif_object head[4];
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};
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struct nv10_fence_priv {
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@ -658,11 +658,8 @@ nv50_ovly_create(struct nvif_device *device, struct nvif_object *disp,
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struct nv50_head {
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struct nouveau_crtc base;
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struct nouveau_bo *image;
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struct nv50_ovly ovly;
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struct nv50_oimm oimm;
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struct nv50_base *_base;
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};
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#define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
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@ -740,40 +737,6 @@ evo_kick(u32 *push, void *evoc)
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*((p)++) = _d; \
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} while(0)
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static bool
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evo_sync_wait(void *data)
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{
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if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000)
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return true;
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usleep_range(1, 2);
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return false;
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}
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static int
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evo_sync(struct drm_device *dev)
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{
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struct nvif_device *device = &nouveau_drm(dev)->device;
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struct nv50_disp *disp = nv50_disp(dev);
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struct nv50_mast *mast = nv50_mast(dev);
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u32 *push = evo_wait(mast, 8);
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if (push) {
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nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
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evo_mthd(push, 0x0084, 1);
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evo_data(push, 0x80000000 | EVO_MAST_NTFY);
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evo_mthd(push, 0x0080, 2);
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evo_data(push, 0x00000000);
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evo_data(push, 0x00000000);
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evo_kick(push, mast);
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if (nvif_msec(device, 2000,
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if (evo_sync_wait(disp->sync))
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break;
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) >= 0)
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return 0;
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}
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return -EBUSY;
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}
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/******************************************************************************
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* Plane
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*****************************************************************************/
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@ -789,8 +752,6 @@ struct nv50_wndw {
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u16 ntfy;
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u16 sema;
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u32 data;
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struct nv50_wndw_atom asy;
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};
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struct nv50_wndw_func {
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@ -1581,151 +1542,6 @@ nv50_base_new(struct nouveau_drm *drm, struct nv50_head *head,
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&base->wndw.notify);
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}
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/******************************************************************************
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* Page flipping channel
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*****************************************************************************/
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struct nouveau_bo *
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nv50_display_crtc_sema(struct drm_device *dev, int crtc)
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{
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return nv50_disp(dev)->sync;
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}
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struct nv50_display_flip {
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struct nv50_disp *disp;
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struct nv50_base *base;
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};
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static bool
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nv50_display_flip_wait(void *data)
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{
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struct nv50_display_flip *flip = data;
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if (nouveau_bo_rd32(flip->disp->sync, flip->base->wndw.sema / 4) ==
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flip->base->wndw.data)
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return true;
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usleep_range(1, 2);
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return false;
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}
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void
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nv50_display_flip_stop(struct drm_crtc *crtc)
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{
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struct nvif_device *device = &nouveau_drm(crtc->dev)->device;
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struct nv50_base *base = nv50_head(crtc)->_base;
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struct nv50_wndw *wndw = &base->wndw;
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struct nv50_wndw_atom *asyw = &wndw->asy;
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struct nv50_display_flip flip = {
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.disp = nv50_disp(crtc->dev),
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.base = base,
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};
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asyw->state.crtc = NULL;
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asyw->state.fb = NULL;
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nv50_wndw_atomic_check(&wndw->plane, &asyw->state);
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nv50_wndw_flush_clr(wndw, 0, true, asyw);
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nvif_msec(device, 2000,
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if (nv50_display_flip_wait(&flip))
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break;
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);
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}
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int
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nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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struct nouveau_channel *chan, u32 swap_interval)
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{
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struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
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struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
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struct nv50_head *head = nv50_head(crtc);
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struct nv50_base *base = nv50_head(crtc)->_base;
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struct nv50_wndw *wndw = &base->wndw;
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struct nv50_wndw_atom *asyw = &wndw->asy;
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int ret;
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if (crtc->primary->fb->width != fb->width ||
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crtc->primary->fb->height != fb->height)
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return -EINVAL;
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if (chan == NULL)
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evo_sync(crtc->dev);
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if (chan && chan->user.oclass < G82_CHANNEL_GPFIFO) {
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ret = RING_SPACE(chan, 8);
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if (ret)
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return ret;
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BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
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OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
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OUT_RING (chan, base->wndw.sema ^ 0x10);
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BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
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OUT_RING (chan, base->wndw.data + 1);
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BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
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OUT_RING (chan, base->wndw.sema);
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OUT_RING (chan, base->wndw.data);
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} else
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if (chan && chan->user.oclass < FERMI_CHANNEL_GPFIFO) {
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u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + base->wndw.sema;
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ret = RING_SPACE(chan, 12);
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if (ret)
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return ret;
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BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
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OUT_RING (chan, chan->vram.handle);
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BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
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OUT_RING (chan, upper_32_bits(addr ^ 0x10));
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OUT_RING (chan, lower_32_bits(addr ^ 0x10));
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OUT_RING (chan, base->wndw.data + 1);
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OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
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BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
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OUT_RING (chan, upper_32_bits(addr));
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OUT_RING (chan, lower_32_bits(addr));
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OUT_RING (chan, base->wndw.data);
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OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
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} else
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if (chan) {
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u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + base->wndw.sema;
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ret = RING_SPACE(chan, 10);
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if (ret)
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return ret;
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BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
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OUT_RING (chan, upper_32_bits(addr ^ 0x10));
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OUT_RING (chan, lower_32_bits(addr ^ 0x10));
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OUT_RING (chan, base->wndw.data + 1);
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OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG |
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NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
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BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
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OUT_RING (chan, upper_32_bits(addr));
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OUT_RING (chan, lower_32_bits(addr));
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OUT_RING (chan, base->wndw.data);
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OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL |
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NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
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}
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if (chan) {
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base->wndw.sema ^= 0x10;
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base->wndw.data++;
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FIRE_RING (chan);
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}
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/* queue the flip */
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asyw->state.crtc = &head->base.base;
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asyw->state.fb = fb;
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asyw->interval = swap_interval;
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asyw->image.handle = nv_fb->r_handle;
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asyw->image.offset = nv_fb->nvbo->bo.offset;
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asyw->sema.handle = base->chan.base.sync.handle;
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asyw->sema.offset = base->wndw.sema;
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asyw->sema.acquire = base->wndw.data++;
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asyw->sema.release = base->wndw.data;
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nv50_wndw_atomic_check(&wndw->plane, &asyw->state);
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asyw->set.sema = true;
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nv50_wndw_flush_set(wndw, 0, asyw);
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nv50_wndw_wait_armed(wndw, asyw);
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nouveau_bo_ref(nv_fb->nvbo, &head->image);
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return 0;
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}
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/******************************************************************************
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* Head
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*****************************************************************************/
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@ -2610,8 +2426,6 @@ nv50_crtc_create(struct drm_device *dev, int index)
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}
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crtc = &head->base.base;
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head->_base = base;
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drm_crtc_init_with_planes(dev, crtc, &base->wndw.plane,
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&curs->wndw.plane, &nv50_crtc_func,
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"head-%d", head->base.index);
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@ -4061,7 +3875,6 @@ nv50_display_fini(struct drm_device *dev)
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int
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nv50_display_init(struct drm_device *dev)
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{
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struct nv50_disp *disp = nv50_disp(dev);
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struct drm_encoder *encoder;
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struct drm_plane *plane;
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struct drm_crtc *crtc;
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@ -4071,13 +3884,6 @@ nv50_display_init(struct drm_device *dev)
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if (!push)
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return -EBUSY;
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list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
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struct nv50_wndw *wndw = &nv50_head(crtc)->_base->wndw;
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nv50_crtc_lut_load(crtc);
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nouveau_bo_wr32(disp->sync, wndw->sema / 4, wndw->data);
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}
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evo_mthd(push, 0x0088, 1);
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evo_data(push, nv50_mast(dev)->base.sync.handle);
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evo_kick(push, nv50_mast(dev));
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@ -4094,6 +3900,10 @@ nv50_display_init(struct drm_device *dev)
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}
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}
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drm_for_each_crtc(crtc, dev) {
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nv50_crtc_lut_load(crtc);
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}
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drm_for_each_plane(plane, dev) {
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struct nv50_wndw *wndw = nv50_wndw(plane);
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if (plane->funcs != &nv50_wndw)
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@ -35,11 +35,4 @@ int nv50_display_create(struct drm_device *);
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void nv50_display_destroy(struct drm_device *);
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int nv50_display_init(struct drm_device *);
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void nv50_display_fini(struct drm_device *);
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void nv50_display_flip_stop(struct drm_crtc *);
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int nv50_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
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struct nouveau_channel *, u32 swap_interval);
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struct nouveau_bo *nv50_display_crtc_sema(struct drm_device *, int head);
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#endif /* __NV50_DISPLAY_H__ */
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@ -35,13 +35,12 @@
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static int
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||||
nv50_fence_context_new(struct nouveau_channel *chan)
|
||||
{
|
||||
struct drm_device *dev = chan->drm->dev;
|
||||
struct nv10_fence_priv *priv = chan->drm->fence;
|
||||
struct nv10_fence_chan *fctx;
|
||||
struct ttm_mem_reg *mem = &priv->bo->bo.mem;
|
||||
u32 start = mem->start * PAGE_SIZE;
|
||||
u32 limit = start + mem->size - 1;
|
||||
int ret, i;
|
||||
int ret;
|
||||
|
||||
fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
|
||||
if (!fctx)
|
||||
|
|
@ -60,23 +59,6 @@ nv50_fence_context_new(struct nouveau_channel *chan)
|
|||
.limit = limit,
|
||||
}, sizeof(struct nv_dma_v0),
|
||||
&fctx->sema);
|
||||
|
||||
/* dma objects for display sync channel semaphore blocks */
|
||||
for (i = 0; !ret && i < dev->mode_config.num_crtc; i++) {
|
||||
struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i);
|
||||
u32 start = bo->bo.mem.start * PAGE_SIZE;
|
||||
u32 limit = start + bo->bo.mem.size - 1;
|
||||
|
||||
ret = nvif_object_init(&chan->user, NvEvoSema0 + i,
|
||||
NV_DMA_IN_MEMORY, &(struct nv_dma_v0) {
|
||||
.target = NV_DMA_V0_TARGET_VRAM,
|
||||
.access = NV_DMA_V0_ACCESS_RDWR,
|
||||
.start = start,
|
||||
.limit = limit,
|
||||
}, sizeof(struct nv_dma_v0),
|
||||
&fctx->head[i]);
|
||||
}
|
||||
|
||||
if (ret)
|
||||
nv10_fence_context_del(chan);
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -28,13 +28,6 @@
|
|||
|
||||
#include "nv50_display.h"
|
||||
|
||||
u64
|
||||
nv84_fence_crtc(struct nouveau_channel *chan, int crtc)
|
||||
{
|
||||
struct nv84_fence_chan *fctx = chan->fence;
|
||||
return fctx->dispc_vma[crtc].offset;
|
||||
}
|
||||
|
||||
static int
|
||||
nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
|
||||
{
|
||||
|
|
@ -110,15 +103,8 @@ nv84_fence_read(struct nouveau_channel *chan)
|
|||
static void
|
||||
nv84_fence_context_del(struct nouveau_channel *chan)
|
||||
{
|
||||
struct drm_device *dev = chan->drm->dev;
|
||||
struct nv84_fence_priv *priv = chan->drm->fence;
|
||||
struct nv84_fence_chan *fctx = chan->fence;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < dev->mode_config.num_crtc; i++) {
|
||||
struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i);
|
||||
nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]);
|
||||
}
|
||||
|
||||
nouveau_bo_wr32(priv->bo, chan->chid * 16 / 4, fctx->base.sequence);
|
||||
nouveau_bo_vma_del(priv->bo, &fctx->vma_gart);
|
||||
|
|
@ -134,7 +120,7 @@ nv84_fence_context_new(struct nouveau_channel *chan)
|
|||
struct nouveau_cli *cli = (void *)chan->user.client;
|
||||
struct nv84_fence_priv *priv = chan->drm->fence;
|
||||
struct nv84_fence_chan *fctx;
|
||||
int ret, i;
|
||||
int ret;
|
||||
|
||||
fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
|
||||
if (!fctx)
|
||||
|
|
@ -154,12 +140,6 @@ nv84_fence_context_new(struct nouveau_channel *chan)
|
|||
&fctx->vma_gart);
|
||||
}
|
||||
|
||||
/* map display semaphore buffers into channel's vm */
|
||||
for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) {
|
||||
struct nouveau_bo *bo = nv50_display_crtc_sema(chan->drm->dev, i);
|
||||
ret = nouveau_bo_vma_add(bo, cli->vm, &fctx->dispc_vma[i]);
|
||||
}
|
||||
|
||||
if (ret)
|
||||
nv84_fence_context_del(chan);
|
||||
return ret;
|
||||
|
|
|
|||
Loading…
Reference in New Issue