drm/nouveau/pmu/gk110: implement gr power-up magic like PGOB on earlier chips
Turns out the PTHERM part of this dance is bracketed by the same PMU fiddling that occurs on GK104/6, let's assume it's also PGOB. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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@ -35,6 +35,7 @@ extern struct nvkm_oclass *gt215_pmu_oclass;
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extern struct nvkm_oclass *gf100_pmu_oclass;
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extern struct nvkm_oclass *gf110_pmu_oclass;
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extern struct nvkm_oclass *gk104_pmu_oclass;
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extern struct nvkm_oclass *gk110_pmu_oclass;
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extern struct nvkm_oclass *gk208_pmu_oclass;
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extern struct nvkm_oclass *gk20a_pmu_oclass;
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@ -202,7 +202,7 @@ gk104_identify(struct nvkm_device *device)
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device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
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device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
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device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
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device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass;
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device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
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device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
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@ -236,7 +236,7 @@ gk104_identify(struct nvkm_device *device)
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device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
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device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
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device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
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device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass;
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device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
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device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
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@ -124,11 +124,8 @@ void gf100_gr_dtor(struct nvkm_object *);
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int gf100_gr_init(struct nvkm_object *);
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void gf100_gr_zbc_init(struct gf100_gr_priv *);
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int gk104_gr_fini(struct nvkm_object *, bool);
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int gk104_gr_init(struct nvkm_object *);
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int gk110_gr_fini(struct nvkm_object *, bool);
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extern struct nvkm_ofuncs gf100_fermi_ofuncs;
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extern struct nvkm_oclass gf100_gr_sclass[];
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@ -173,43 +173,6 @@ gk110_gr_pack_mmio[] = {
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* PGRAPH engine/subdev functions
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******************************************************************************/
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int
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gk110_gr_fini(struct nvkm_object *object, bool suspend)
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{
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struct gf100_gr_priv *priv = (void *)object;
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static const struct {
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u32 addr;
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u32 data;
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} magic[] = {
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{ 0x020520, 0xfffffffc },
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{ 0x020524, 0xfffffffe },
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{ 0x020524, 0xfffffffc },
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{ 0x020524, 0xfffffff8 },
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{ 0x020524, 0xffffffe0 },
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{ 0x020530, 0xfffffffe },
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{ 0x02052c, 0xfffffffa },
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{ 0x02052c, 0xfffffff0 },
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{ 0x02052c, 0xffffffc0 },
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{ 0x02052c, 0xffffff00 },
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{ 0x02052c, 0xfffffc00 },
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{ 0x02052c, 0xfffcfc00 },
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{ 0x02052c, 0xfff0fc00 },
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{ 0x02052c, 0xff80fc00 },
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{ 0x020528, 0xfffffffe },
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{ 0x020528, 0xfffffffc },
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};
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int i;
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nv_mask(priv, 0x000200, 0x08001000, 0x00000000);
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nv_mask(priv, 0x0206b4, 0x00000000, 0x00000000);
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for (i = 0; i < ARRAY_SIZE(magic); i++) {
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nv_wr32(priv, magic[i].addr, magic[i].data);
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nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000);
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}
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return nvkm_gr_fini(&priv->base, suspend);
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}
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#include "fuc/hubgk110.fuc3.h"
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struct gf100_gr_ucode
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@ -237,7 +200,7 @@ gk110_gr_oclass = &(struct gf100_gr_oclass) {
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.ctor = gf100_gr_ctor,
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.dtor = gf100_gr_dtor,
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.init = gk104_gr_init,
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.fini = gk110_gr_fini,
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.fini = _nvkm_gr_fini,
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},
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.cclass = &gk110_grctx_oclass,
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.sclass = gk110_gr_sclass,
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@ -105,7 +105,7 @@ gk110b_gr_oclass = &(struct gf100_gr_oclass) {
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.ctor = gf100_gr_ctor,
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.dtor = gf100_gr_dtor,
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.init = gk104_gr_init,
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.fini = gk110_gr_fini,
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.fini = _nvkm_gr_fini,
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},
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.cclass = &gk110b_grctx_oclass,
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.sclass = gk110_gr_sclass,
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@ -4,5 +4,6 @@ nvkm-y += nvkm/subdev/pmu/gt215.o
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nvkm-y += nvkm/subdev/pmu/gf100.o
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nvkm-y += nvkm/subdev/pmu/gf110.o
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nvkm-y += nvkm/subdev/pmu/gk104.o
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nvkm-y += nvkm/subdev/pmu/gk110.o
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nvkm-y += nvkm/subdev/pmu/gk208.o
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nvkm-y += nvkm/subdev/pmu/gk20a.o
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@ -0,0 +1,95 @@
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/*
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* Copyright 2015 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#define gf110_pmu_code gk110_pmu_code
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#define gf110_pmu_data gk110_pmu_data
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#include "priv.h"
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#include "fuc/gf110.fuc4.h"
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#include <subdev/timer.h>
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static void
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gk110_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
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{
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static const struct {
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u32 addr;
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u32 data;
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} magic[] = {
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{ 0x020520, 0xfffffffc },
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{ 0x020524, 0xfffffffe },
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{ 0x020524, 0xfffffffc },
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{ 0x020524, 0xfffffff8 },
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{ 0x020524, 0xffffffe0 },
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{ 0x020530, 0xfffffffe },
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{ 0x02052c, 0xfffffffa },
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{ 0x02052c, 0xfffffff0 },
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{ 0x02052c, 0xffffffc0 },
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{ 0x02052c, 0xffffff00 },
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{ 0x02052c, 0xfffffc00 },
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{ 0x02052c, 0xfffcfc00 },
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{ 0x02052c, 0xfff0fc00 },
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{ 0x02052c, 0xff80fc00 },
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{ 0x020528, 0xfffffffe },
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{ 0x020528, 0xfffffffc },
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};
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int i;
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nv_mask(pmu, 0x000200, 0x00001000, 0x00000000);
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nv_rd32(pmu, 0x000200);
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nv_mask(pmu, 0x000200, 0x08000000, 0x08000000);
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msleep(50);
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nv_mask(pmu, 0x10a78c, 0x00000002, 0x00000002);
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nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000001);
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nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000000);
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nv_mask(pmu, 0x0206b4, 0x00000000, 0x00000000);
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for (i = 0; i < ARRAY_SIZE(magic); i++) {
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nv_wr32(pmu, magic[i].addr, magic[i].data);
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nv_wait(pmu, magic[i].addr, 0x80000000, 0x00000000);
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}
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nv_mask(pmu, 0x10a78c, 0x00000002, 0x00000000);
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nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000001);
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nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000000);
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nv_mask(pmu, 0x000200, 0x08000000, 0x00000000);
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nv_mask(pmu, 0x000200, 0x00001000, 0x00001000);
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nv_rd32(pmu, 0x000200);
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}
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struct nvkm_oclass *
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gk110_pmu_oclass = &(struct nvkm_pmu_impl) {
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.base.handle = NV_SUBDEV(PMU, 0xf0),
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.base.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = _nvkm_pmu_ctor,
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.dtor = _nvkm_pmu_dtor,
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.init = _nvkm_pmu_init,
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.fini = _nvkm_pmu_fini,
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},
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.code.data = gk110_pmu_code,
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.code.size = sizeof(gk110_pmu_code),
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.data.data = gk110_pmu_data,
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.data.size = sizeof(gk110_pmu_data),
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.pgob = gk110_pmu_pgob,
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}.base;
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