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riscv: remove unreachable big endian code 

RISC-V is always little endian.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Christoph Hellwig 2019-04-15 11:14:34 +02:00 committed by Palmer Dabbelt
parent 5cfade5fdc
commit e28dcc77e8
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GPG Key ID: EF4CA1502CCBAB41
2 changed files with 1 additions and 14 deletions
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6
arch/riscv/include/asm/elf.h
View File

@ -27,13 +27,7 @@
#define ELF_CLASS ELFCLASS32
#endif
#if defined(__LITTLE_ENDIAN)
#define ELF_DATA ELFDATA2LSB
#elif defined(__BIG_ENDIAN)
#define ELF_DATA ELFDATA2MSB
#else
#error "Unknown endianness"
#endif
/*
* This is used to ensure we don't load something for the wrong architecture.

9
arch/riscv/include/asm/uaccess.h
View File

@ -101,15 +101,8 @@ static inline int __access_ok(unsigned long addr, unsigned long size)
* on our cache or tlb entries.
*/
#if defined(__LITTLE_ENDIAN)
#define __MSW 1
#define __LSW 0
#elif defined(__BIG_ENDIAN)
#define __MSW 0
#define __LSW 1
#else
#error "Unknown endianness"
#endif
#define __MSW 1
/*
* The "__xxx" versions of the user access functions do not verify the address