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arm64: dts: Convert to the hierarchical CPU topology layout for MSM8916 

To enable the OS to better support PSCI OS initiated CPU suspend mode,
let's convert from the flattened layout to the hierarchical layout.

In the hierarchical layout, let's create a power domain provider per CPU
and describe the idle states for each CPU inside the power domain provider
node. To group the CPUs into a cluster, let's add another power domain
provider and make it act as the master domain. Note that, the CPU's idle
states remains compatible with "arm,idle-state", while the cluster's idle
state becomes compatible with "domain-idle-state".

Co-developed-by: Lina Iyer <lina.iyer@linaro.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
This commit is contained in:
Ulf Hansson 2019-10-10 12:01:48 +02:00
parent a65a397f24
commit e371315568
1 changed files with 53 additions and 4 deletions
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57
arch/arm64/boot/dts/qcom/msm8916.dtsi
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@ -102,10 +102,11 @@ CPU0: cpu@0 {
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&apcs>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
};
CPU1: cpu@1 {
@ -114,10 +115,11 @@ CPU1: cpu@1 {
reg = <0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&apcs>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
};
CPU2: cpu@2 {
@ -126,10 +128,11 @@ CPU2: cpu@2 {
reg = <0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&apcs>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
};
CPU3: cpu@3 {
@ -138,10 +141,11 @@ CPU3: cpu@3 {
reg = <0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&apcs>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
};
L2_0: l2-cache {
@ -161,12 +165,57 @@ CPU_SLEEP_0: cpu-sleep-0 {
min-residency-us = <2000>;
local-timer-stop;
};
CLUSTER_RET: cluster-retention {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000012>;
entry-latency-us = <500>;
exit-latency-us = <500>;
min-residency-us = <2000>;
};
CLUSTER_PWRDN: cluster-gdhs {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000032>;
entry-latency-us = <2000>;
exit-latency-us = <2000>;
min-residency-us = <6000>;
};
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: cpu-pd0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&CPU_SLEEP_0>;
};
CPU_PD1: cpu-pd1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&CPU_SLEEP_0>;
};
CPU_PD2: cpu-pd2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&CPU_SLEEP_0>;
};
CPU_PD3: cpu-pd3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&CPU_SLEEP_0>;
};
CLUSTER_PD: cluster-pd {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
};
};
pmu {