p71924506
/
linux_old1
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Merge branch 'drm-fixes-3.16' of git://people.freedesktop.org/~agd5f/linux 

misc fixes, output fixes for 4k monitor, dpm lockup fixes

* 'drm-fixes-3.16' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: page table BOs are kernel allocations
  drm/radeon/cik: fix typo in EOP packet
  drm/radeon: Track the status of a page flip more explicitly
  drm/radeon/dpm: fix vddci setup typo on cayman
  drm/radeon/dpm: fix typo in vddci setup for eg/btc
  drm/radeon: use RADEON_MAX_CRTCS, RADEON_MAX_AFMT_BLOCKS (v2)
  drm/radeon: Use only one line for whole DPCD debug output
  drm/radeon: add a module parameter to control deep color support
  drm/radeon: enable bapm by default on desktop TN/RL boards
  drm/radeon: enable bapm by default on KV/KB
  drm/radeon: only apply bapm changes for AC power on ARUBA
  drm/radeon: adjust default dispclk on DCE6 (v2)
This commit is contained in:
Dave Airlie 2014-07-03 07:55:32 +10:00
parent 186026874c 7dae77f880
commit e55a379827
14 changed files with 70 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/gpu/drm/radeon/atombios_dp.c
View File

@ -403,16 +403,18 @@ bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
{ {
struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
u8 msg[DP_DPCD_SIZE]; u8 msg[DP_DPCD_SIZE];
int ret, i; int ret;
char dpcd_hex_dump[DP_DPCD_SIZE * 3];
ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg, ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
DP_DPCD_SIZE); DP_DPCD_SIZE);
if (ret > 0) { if (ret > 0) {
memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
DRM_DEBUG_KMS("DPCD: ");
for (i = 0; i < DP_DPCD_SIZE; i++) hex_dump_to_buffer(dig_connector->dpcd, sizeof(dig_connector->dpcd),
DRM_DEBUG_KMS("%02x ", msg[i]); 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
DRM_DEBUG_KMS("\n"); DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
radeon_dp_probe_oui(radeon_connector); radeon_dp_probe_oui(radeon_connector);

2
drivers/gpu/drm/radeon/cikd.h
View File

@ -1752,12 +1752,12 @@
#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
#define EOP_TCL1_ACTION_EN (1 << 16) #define EOP_TCL1_ACTION_EN (1 << 16)
#define EOP_TC_ACTION_EN (1 << 17) /* L2 */ #define EOP_TC_ACTION_EN (1 << 17) /* L2 */
#define EOP_TCL2_VOLATILE (1 << 24)
#define EOP_CACHE_POLICY(x) ((x) << 25) #define EOP_CACHE_POLICY(x) ((x) << 25)
/* 0 - LRU /* 0 - LRU
* 1 - Stream * 1 - Stream
* 2 - Bypass * 2 - Bypass
*/ */
#define EOP_TCL2_VOLATILE (1 << 27)
#define DATA_SEL(x) ((x) << 29) #define DATA_SEL(x) ((x) << 29)
/* 0 - discard /* 0 - discard
* 1 - send low 32bit data * 1 - send low 32bit data

2
drivers/gpu/drm/radeon/cypress_dpm.c
View File

@ -1551,7 +1551,7 @@ int cypress_populate_smc_voltage_tables(struct radeon_device *rdev,
table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDCI] = 0; table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDCI] = 0;
table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDCI] = table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDCI] =
cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
} }
return 0; return 0;

2
drivers/gpu/drm/radeon/kv_dpm.c
View File

@ -2726,7 +2726,7 @@ int kv_dpm_init(struct radeon_device *rdev)
pi->caps_sclk_ds = true; pi->caps_sclk_ds = true;
pi->enable_auto_thermal_throttling = true; pi->enable_auto_thermal_throttling = true;
pi->disable_nb_ps3_in_battery = false; pi->disable_nb_ps3_in_battery = false;
pi->bapm_enable = false; pi->bapm_enable = true;
pi->voltage_drop_t = 0; pi->voltage_drop_t = 0;
pi->caps_sclk_throttle_low_notification = false; pi->caps_sclk_throttle_low_notification = false;
pi->caps_fps = false; /* true? */ pi->caps_fps = false; /* true? */

2
drivers/gpu/drm/radeon/ni_dpm.c
View File

@ -1315,7 +1315,7 @@ static void ni_populate_smc_voltage_tables(struct radeon_device *rdev,
table->voltageMaskTable.highMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] = 0; table->voltageMaskTable.highMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] = 0;
table->voltageMaskTable.lowMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] = table->voltageMaskTable.lowMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] =
cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
} }
} }

5
drivers/gpu/drm/radeon/radeon.h
View File

@ -102,6 +102,7 @@ extern int radeon_runtime_pm;
extern int radeon_hard_reset; extern int radeon_hard_reset;
extern int radeon_vm_size; extern int radeon_vm_size;
extern int radeon_vm_block_size; extern int radeon_vm_block_size;
extern int radeon_deep_color;
/* /*
* Copy from radeon_drv.h so we don't have to include both and have conflicting * Copy from radeon_drv.h so we don't have to include both and have conflicting
@ -749,10 +750,6 @@ union radeon_irq_stat_regs {
struct cik_irq_stat_regs cik; struct cik_irq_stat_regs cik;
}; };
#define RADEON_MAX_HPD_PINS 7
#define RADEON_MAX_CRTCS 6
#define RADEON_MAX_AFMT_BLOCKS 7
struct radeon_irq { struct radeon_irq {
bool installed; bool installed;
spinlock_t lock; spinlock_t lock;

10
drivers/gpu/drm/radeon/radeon_atombios.c
View File

@ -1227,11 +1227,19 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
rdev->clock.default_dispclk = rdev->clock.default_dispclk =
le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
if (rdev->clock.default_dispclk == 0) { if (rdev->clock.default_dispclk == 0) {
if (ASIC_IS_DCE5(rdev)) if (ASIC_IS_DCE6(rdev))
rdev->clock.default_dispclk = 60000; /* 600 Mhz */
else if (ASIC_IS_DCE5(rdev))
rdev->clock.default_dispclk = 54000; /* 540 Mhz */ rdev->clock.default_dispclk = 54000; /* 540 Mhz */
else else
rdev->clock.default_dispclk = 60000; /* 600 Mhz */ rdev->clock.default_dispclk = 60000; /* 600 Mhz */
} }
/* set a reasonable default for DP */
if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
rdev->clock.default_dispclk / 100);
rdev->clock.default_dispclk = 60000;
}
rdev->clock.dp_extclk = rdev->clock.dp_extclk =
le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
rdev->clock.current_dispclk = rdev->clock.default_dispclk; rdev->clock.current_dispclk = rdev->clock.default_dispclk;

3
drivers/gpu/drm/radeon/radeon_connectors.c
View File

@ -199,6 +199,9 @@ int radeon_get_monitor_bpc(struct drm_connector *connector)
} }
} }
if ((radeon_deep_color == 0) && (bpc > 8))
bpc = 8;
DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
connector->name, connector->display_info.bpc, bpc); connector->name, connector->display_info.bpc, bpc);

19
drivers/gpu/drm/radeon/radeon_display.c
View File

@ -285,7 +285,6 @@ static void radeon_unpin_work_func(struct work_struct *__work)
void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id) void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
{ {
struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
struct radeon_flip_work *work;
unsigned long flags; unsigned long flags;
u32 update_pending; u32 update_pending;
int vpos, hpos; int vpos, hpos;
@ -295,8 +294,11 @@ void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
return; return;
spin_lock_irqsave(&rdev->ddev->event_lock, flags); spin_lock_irqsave(&rdev->ddev->event_lock, flags);
work = radeon_crtc->flip_work; if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
if (work == NULL) { DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
"RADEON_FLIP_SUBMITTED(%d)\n",
radeon_crtc->flip_status,
RADEON_FLIP_SUBMITTED);
spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
return; return;
} }
@ -344,12 +346,17 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
spin_lock_irqsave(&rdev->ddev->event_lock, flags); spin_lock_irqsave(&rdev->ddev->event_lock, flags);
work = radeon_crtc->flip_work; work = radeon_crtc->flip_work;
if (work == NULL) { if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
"RADEON_FLIP_SUBMITTED(%d)\n",
radeon_crtc->flip_status,
RADEON_FLIP_SUBMITTED);
spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
return; return;
} }
/* Pageflip completed. Clean up. */ /* Pageflip completed. Clean up. */
radeon_crtc->flip_status = RADEON_FLIP_NONE;
radeon_crtc->flip_work = NULL; radeon_crtc->flip_work = NULL;
/* wakeup userspace */ /* wakeup userspace */
@ -476,6 +483,7 @@ static void radeon_flip_work_func(struct work_struct *__work)
/* do the flip (mmio) */ /* do the flip (mmio) */
radeon_page_flip(rdev, radeon_crtc->crtc_id, base); radeon_page_flip(rdev, radeon_crtc->crtc_id, base);
radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
spin_unlock_irqrestore(&crtc->dev->event_lock, flags); spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
up_read(&rdev->exclusive_lock); up_read(&rdev->exclusive_lock);
@ -544,7 +552,7 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc,
/* We borrow the event spin lock for protecting flip_work */ /* We borrow the event spin lock for protecting flip_work */
spin_lock_irqsave(&crtc->dev->event_lock, flags); spin_lock_irqsave(&crtc->dev->event_lock, flags);
if (radeon_crtc->flip_work) { if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
spin_unlock_irqrestore(&crtc->dev->event_lock, flags); spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
@ -552,6 +560,7 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc,
kfree(work); kfree(work);
return -EBUSY; return -EBUSY;
} }
radeon_crtc->flip_status = RADEON_FLIP_PENDING;
radeon_crtc->flip_work = work; radeon_crtc->flip_work = work;
/* update crtc fb */ /* update crtc fb */

4
drivers/gpu/drm/radeon/radeon_drv.c
View File

@ -175,6 +175,7 @@ int radeon_runtime_pm = -1;
int radeon_hard_reset = 0; int radeon_hard_reset = 0;
int radeon_vm_size = 4096; int radeon_vm_size = 4096;
int radeon_vm_block_size = 9; int radeon_vm_block_size = 9;
int radeon_deep_color = 0;
MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
module_param_named(no_wb, radeon_no_wb, int, 0444); module_param_named(no_wb, radeon_no_wb, int, 0444);
@ -248,6 +249,9 @@ module_param_named(vm_size, radeon_vm_size, int, 0444);
MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default 9)"); MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default 9)");
module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
module_param_named(deep_color, radeon_deep_color, int, 0444);
static struct pci_device_id pciidlist[] = { static struct pci_device_id pciidlist[] = {
radeon_PCI_IDS radeon_PCI_IDS
}; };

15
drivers/gpu/drm/radeon/radeon_mode.h
View File

@ -46,6 +46,10 @@ struct radeon_device;
#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
#define RADEON_MAX_HPD_PINS 7
#define RADEON_MAX_CRTCS 6
#define RADEON_MAX_AFMT_BLOCKS 7
enum radeon_rmx_type { enum radeon_rmx_type {
RMX_OFF, RMX_OFF,
RMX_FULL, RMX_FULL,
@ -233,8 +237,8 @@ struct radeon_mode_info {
struct card_info *atom_card_info; struct card_info *atom_card_info;
enum radeon_connector_table connector_table; enum radeon_connector_table connector_table;
bool mode_config_initialized; bool mode_config_initialized;
struct radeon_crtc *crtcs[6]; struct radeon_crtc *crtcs[RADEON_MAX_CRTCS];
struct radeon_afmt *afmt[7]; struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS];
/* DVI-I properties */ /* DVI-I properties */
struct drm_property *coherent_mode_property; struct drm_property *coherent_mode_property;
/* DAC enable load detect */ /* DAC enable load detect */
@ -302,6 +306,12 @@ struct radeon_atom_ss {
uint16_t amount; uint16_t amount;
}; };
enum radeon_flip_status {
RADEON_FLIP_NONE,
RADEON_FLIP_PENDING,
RADEON_FLIP_SUBMITTED
};
struct radeon_crtc { struct radeon_crtc {
struct drm_crtc base; struct drm_crtc base;
int crtc_id; int crtc_id;
@ -327,6 +337,7 @@ struct radeon_crtc {
/* page flipping */ /* page flipping */
struct workqueue_struct *flip_queue; struct workqueue_struct *flip_queue;
struct radeon_flip_work *flip_work; struct radeon_flip_work *flip_work;
enum radeon_flip_status flip_status;
/* pll sharing */ /* pll sharing */
struct radeon_atom_ss ss; struct radeon_atom_ss ss;
bool ss_enabled; bool ss_enabled;

6
drivers/gpu/drm/radeon/radeon_pm.c
View File

@ -73,8 +73,10 @@ void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
rdev->pm.dpm.ac_power = true; rdev->pm.dpm.ac_power = true;
else else
rdev->pm.dpm.ac_power = false; rdev->pm.dpm.ac_power = false;
if (rdev->asic->dpm.enable_bapm) if (rdev->family == CHIP_ARUBA) {
radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power); if (rdev->asic->dpm.enable_bapm)
radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
}
mutex_unlock(&rdev->pm.mutex); mutex_unlock(&rdev->pm.mutex);
} else if (rdev->pm.pm_method == PM_METHOD_PROFILE) { } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
if (rdev->pm.profile == PM_PROFILE_AUTO) { if (rdev->pm.profile == PM_PROFILE_AUTO) {

4
drivers/gpu/drm/radeon/radeon_vm.c
View File

@ -495,7 +495,7 @@ int radeon_vm_bo_set_addr(struct radeon_device *rdev,
mutex_unlock(&vm->mutex); mutex_unlock(&vm->mutex);
r = radeon_bo_create(rdev, RADEON_VM_PTE_COUNT * 8, r = radeon_bo_create(rdev, RADEON_VM_PTE_COUNT * 8,
RADEON_GPU_PAGE_SIZE, false, RADEON_GPU_PAGE_SIZE, true,
RADEON_GEM_DOMAIN_VRAM, NULL, &pt); RADEON_GEM_DOMAIN_VRAM, NULL, &pt);
if (r) if (r)
return r; return r;
@ -992,7 +992,7 @@ int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
return -ENOMEM; return -ENOMEM;
} }
r = radeon_bo_create(rdev, pd_size, align, false, r = radeon_bo_create(rdev, pd_size, align, true,
RADEON_GEM_DOMAIN_VRAM, NULL, RADEON_GEM_DOMAIN_VRAM, NULL,
&vm->page_directory); &vm->page_directory);
if (r) if (r)

10
drivers/gpu/drm/radeon/trinity_dpm.c
View File

@ -1874,7 +1874,15 @@ int trinity_dpm_init(struct radeon_device *rdev)
for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
pi->at[i] = TRINITY_AT_DFLT; pi->at[i] = TRINITY_AT_DFLT;
pi->enable_bapm = false; /* There are stability issues reported on latops with
* bapm installed when switching between AC and battery
* power. At the same time, some desktop boards hang
* if it's not enabled and dpm is enabled.
*/
if (rdev->flags & RADEON_IS_MOBILITY)
pi->enable_bapm = false;
else
pi->enable_bapm = true;
pi->enable_nbps_policy = true; pi->enable_nbps_policy = true;
pi->enable_sclk_ds = true; pi->enable_sclk_ds = true;
pi->enable_gfx_power_gating = true; pi->enable_gfx_power_gating = true;