scsi: mpt3sas: Introduce function to clone mpi request.
1) Added function _base_clone_mpi_to_sys_mem to clone MPI request into system BAR0 mapped region. 2) Separate out MPI Endpoint IO submissions to function _base_put_smid_mpi_ep_scsi_io. 3) MPI EP requests are submitted in two 32 bit MMIO writes. from _base_mpi_ep_writeq. For 32 bit Arch,_base_writeq function is identical to _base_mpi_ep_writeq, Removed duplicate code as suggested. Signed-off-by: Suganath Prabu S <suganath-prabu.subramani@broadcom.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Suganath Prabu Subramani
Martin K. Petersen
parent
182ac784b4
commit
e574743936
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@ -125,6 +125,25 @@ _scsih_set_fwfault_debug(const char *val, const struct kernel_param *kp)
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module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
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param_get_int, &mpt3sas_fwfault_debug, 0644);
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/**
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* _base_clone_mpi_to_sys_mem - Writes/copies MPI frames
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* to system/BAR0 region.
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*
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* @dst_iomem: Pointer to the destinaltion location in BAR0 space.
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* @src: Pointer to the Source data.
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* @size: Size of data to be copied.
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*/
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static void
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_base_clone_mpi_to_sys_mem(void *dst_iomem, void *src, u32 size)
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{
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int i;
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u32 *src_virt_mem = (u32 *)src;
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for (i = 0; i < size/4; i++)
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writel((u32)src_virt_mem[i],
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(void __iomem *)dst_iomem + (i * 4));
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}
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/**
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* _base_clone_to_sys_mem - Writes/copies data to system/BAR0 region
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*
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@ -3267,6 +3286,29 @@ mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
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spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
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}
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/**
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* _base_mpi_ep_writeq - 32 bit write to MMIO
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* @b: data payload
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* @addr: address in MMIO space
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* @writeq_lock: spin lock
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*
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* This special handling for MPI EP to take care of 32 bit
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* environment where its not quarenteed to send the entire word
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* in one transfer.
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*/
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static inline void
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_base_mpi_ep_writeq(__u64 b, volatile void __iomem *addr,
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spinlock_t *writeq_lock)
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{
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unsigned long flags;
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__u64 data_out = cpu_to_le64(b);
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spin_lock_irqsave(writeq_lock, flags);
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writel((u32)(data_out), addr);
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writel((u32)(data_out >> 32), (addr + 4));
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spin_unlock_irqrestore(writeq_lock, flags);
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}
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/**
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* _base_writeq - 64 bit write to MMIO
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* @ioc: per adapter object
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@ -3288,16 +3330,40 @@ _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
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static inline void
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_base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
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{
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unsigned long flags;
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__u64 data_out = cpu_to_le64(b);
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spin_lock_irqsave(writeq_lock, flags);
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writel((u32)(data_out), addr);
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writel((u32)(data_out >> 32), (addr + 4));
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spin_unlock_irqrestore(writeq_lock, flags);
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_base_mpi_ep_writeq(b, addr, writeq_lock);
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}
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#endif
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/**
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* _base_put_smid_mpi_ep_scsi_io - send SCSI_IO request to firmware
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* @ioc: per adapter object
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* @smid: system request message index
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* @handle: device handle
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*
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* Return nothing.
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*/
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static void
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_base_put_smid_mpi_ep_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
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{
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Mpi2RequestDescriptorUnion_t descriptor;
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u64 *request = (u64 *)&descriptor;
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void *mpi_req_iomem;
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__le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid);
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_clone_sg_entries(ioc, (void *) mfp, smid);
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mpi_req_iomem = (void *)ioc->chip +
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MPI_FRAME_START_OFFSET + (smid * ioc->request_sz);
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_base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
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ioc->request_sz);
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descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
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descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
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descriptor.SCSIIO.SMID = cpu_to_le16(smid);
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descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
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descriptor.SCSIIO.LMID = 0;
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_base_mpi_ep_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
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&ioc->scsi_lookup_lock);
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}
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/**
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* _base_put_smid_scsi_io - send SCSI_IO request to firmware
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* @ioc: per adapter object
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@ -3359,7 +3425,23 @@ _base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid,
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u16 msix_task)
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{
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Mpi2RequestDescriptorUnion_t descriptor;
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u64 *request = (u64 *)&descriptor;
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void *mpi_req_iomem;
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u64 *request;
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if (ioc->is_mcpu_endpoint) {
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MPI2RequestHeader_t *request_hdr;
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__le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid);
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request_hdr = (MPI2RequestHeader_t *)mfp;
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/* TBD 256 is offset within sys register. */
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mpi_req_iomem = (void *)ioc->chip + MPI_FRAME_START_OFFSET
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+ (smid * ioc->request_sz);
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_base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
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ioc->request_sz);
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}
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request = (u64 *)&descriptor;
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descriptor.HighPriority.RequestFlags =
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MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
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@ -3367,8 +3449,13 @@ _base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid,
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descriptor.HighPriority.SMID = cpu_to_le16(smid);
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descriptor.HighPriority.LMID = 0;
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descriptor.HighPriority.Reserved1 = 0;
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_base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
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&ioc->scsi_lookup_lock);
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if (ioc->is_mcpu_endpoint)
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_base_mpi_ep_writeq(*request,
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&ioc->chip->RequestDescriptorPostLow,
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&ioc->scsi_lookup_lock);
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else
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_base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
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&ioc->scsi_lookup_lock);
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}
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/**
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@ -3406,15 +3493,35 @@ static void
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_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
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{
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Mpi2RequestDescriptorUnion_t descriptor;
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u64 *request = (u64 *)&descriptor;
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void *mpi_req_iomem;
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u64 *request;
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MPI2RequestHeader_t *request_hdr;
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if (ioc->is_mcpu_endpoint) {
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__le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid);
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request_hdr = (MPI2RequestHeader_t *)mfp;
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_clone_sg_entries(ioc, (void *) mfp, smid);
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/* TBD 256 is offset within sys register */
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mpi_req_iomem = (void *)ioc->chip +
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MPI_FRAME_START_OFFSET + (smid * ioc->request_sz);
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_base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
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ioc->request_sz);
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}
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request = (u64 *)&descriptor;
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descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
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descriptor.Default.MSIxIndex = _base_get_msix_index(ioc);
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descriptor.Default.SMID = cpu_to_le16(smid);
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descriptor.Default.LMID = 0;
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descriptor.Default.DescriptorTypeDependent = 0;
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_base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
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&ioc->scsi_lookup_lock);
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if (ioc->is_mcpu_endpoint)
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_base_mpi_ep_writeq(*request,
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&ioc->chip->RequestDescriptorPostLow,
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&ioc->scsi_lookup_lock);
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else
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_base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
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&ioc->scsi_lookup_lock);
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}
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/**
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@ -3508,7 +3615,7 @@ _base_put_smid_nvme_encap_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid)
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/**
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* _base_put_smid_default - Default, primarily used for config pages
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* use Atomic Request Descriptor
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* use Atomic Request Descriptor
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* @ioc: per adapter object
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* @smid: system request message index
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*
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@ -6333,7 +6440,10 @@ mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
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ioc->put_smid_nvme_encap = &_base_put_smid_nvme_encap_atomic;
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} else {
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ioc->put_smid_default = &_base_put_smid_default;
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ioc->put_smid_scsi_io = &_base_put_smid_scsi_io;
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if (ioc->is_mcpu_endpoint)
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ioc->put_smid_scsi_io = &_base_put_smid_mpi_ep_scsi_io;
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else
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ioc->put_smid_scsi_io = &_base_put_smid_scsi_io;
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ioc->put_smid_fast_path = &_base_put_smid_fast_path;
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ioc->put_smid_hi_priority = &_base_put_smid_hi_priority;
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ioc->put_smid_nvme_encap = &_base_put_smid_nvme_encap;
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