media: cxd2880: Add tuner part of the driver
This part of the driver has the main routines to handle the tuner and demodulator functionality. The tnrdmd_mon.* files have monitor functions for the driver. This is part of the Sony CXD2880 DVB-T2/T tuner + demodulator driver. Signed-off-by: Yasunari Takiguchi <Yasunari.Takiguchi@sony.com> Signed-off-by: Masayuki Yamamoto <Masayuki.Yamamoto@sony.com> Signed-off-by: Hideki Nozawa <Hideki.Nozawa@sony.com> Signed-off-by: Kota Yonezawa <Kota.Yonezawa@sony.com> Signed-off-by: Toshihiko Matsumoto <Toshihiko.Matsumoto@sony.com> Signed-off-by: Satoshi Watanabe <Satoshi.C.Watanabe@sony.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
This commit is contained in:
Yasunari Takiguchi
Mauro Carvalho Chehab
parent
4e67e6cb06
commit
e5835488c2
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@ -0,0 +1,29 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* cxd2880_dtv.h
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* Sony CXD2880 DVB-T2/T tuner + demodulator driver
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* DTV related definitions
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*
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* Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation
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*/
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#ifndef CXD2880_DTV_H
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#define CXD2880_DTV_H
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enum cxd2880_dtv_sys {
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CXD2880_DTV_SYS_UNKNOWN,
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CXD2880_DTV_SYS_DVBT,
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CXD2880_DTV_SYS_DVBT2,
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CXD2880_DTV_SYS_ANY
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};
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enum cxd2880_dtv_bandwidth {
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CXD2880_DTV_BW_UNKNOWN = 0,
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CXD2880_DTV_BW_1_7_MHZ = 1,
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CXD2880_DTV_BW_5_MHZ = 5,
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CXD2880_DTV_BW_6_MHZ = 6,
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CXD2880_DTV_BW_7_MHZ = 7,
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CXD2880_DTV_BW_8_MHZ = 8
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};
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#endif
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,365 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* cxd2880_tnrdmd.h
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* Sony CXD2880 DVB-T2/T tuner + demodulator driver
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* common control interface
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*
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* Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation
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*/
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#ifndef CXD2880_TNRDMD_H
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#define CXD2880_TNRDMD_H
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#include <linux/atomic.h>
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#include "cxd2880_common.h"
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#include "cxd2880_io.h"
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#include "cxd2880_dtv.h"
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#include "cxd2880_dvbt.h"
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#include "cxd2880_dvbt2.h"
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#define CXD2880_TNRDMD_MAX_CFG_MEM_COUNT 100
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#define slvt_unfreeze_reg(tnr_dmd) ((void)((tnr_dmd)->io->write_reg\
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((tnr_dmd)->io, CXD2880_IO_TGT_DMD, 0x01, 0x00)))
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_UNDERFLOW 0x0001
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_OVERFLOW 0x0002
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_ALMOST_EMPTY 0x0004
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_ALMOST_FULL 0x0008
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_RRDY 0x0010
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_ILLEGAL_COMMAND 0x0020
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_ILLEGAL_ACCESS 0x0040
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_CPU_ERROR 0x0100
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_LOCK 0x0200
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_INV_LOCK 0x0400
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_NOOFDM 0x0800
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_EWS 0x1000
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_EEW 0x2000
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#define CXD2880_TNRDMD_INTERRUPT_TYPE_FEC_FAIL 0x4000
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#define CXD2880_TNRDMD_INTERRUPT_LOCK_SEL_L1POST_OK 0x01
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#define CXD2880_TNRDMD_INTERRUPT_LOCK_SEL_DMD_LOCK 0x02
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#define CXD2880_TNRDMD_INTERRUPT_LOCK_SEL_TS_LOCK 0x04
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enum cxd2880_tnrdmd_chip_id {
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CXD2880_TNRDMD_CHIP_ID_UNKNOWN = 0x00,
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CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_0X = 0x62,
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CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_11 = 0x6a
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};
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#define CXD2880_TNRDMD_CHIP_ID_VALID(chip_id) \
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(((chip_id) == CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_0X) || \
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((chip_id) == CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_11))
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enum cxd2880_tnrdmd_state {
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CXD2880_TNRDMD_STATE_UNKNOWN,
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CXD2880_TNRDMD_STATE_SLEEP,
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CXD2880_TNRDMD_STATE_ACTIVE,
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CXD2880_TNRDMD_STATE_INVALID
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};
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enum cxd2880_tnrdmd_divermode {
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CXD2880_TNRDMD_DIVERMODE_SINGLE,
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CXD2880_TNRDMD_DIVERMODE_MAIN,
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CXD2880_TNRDMD_DIVERMODE_SUB
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};
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enum cxd2880_tnrdmd_clockmode {
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CXD2880_TNRDMD_CLOCKMODE_UNKNOWN,
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CXD2880_TNRDMD_CLOCKMODE_A,
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CXD2880_TNRDMD_CLOCKMODE_B,
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CXD2880_TNRDMD_CLOCKMODE_C
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};
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enum cxd2880_tnrdmd_tsout_if {
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CXD2880_TNRDMD_TSOUT_IF_TS,
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CXD2880_TNRDMD_TSOUT_IF_SPI,
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CXD2880_TNRDMD_TSOUT_IF_SDIO
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};
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enum cxd2880_tnrdmd_xtal_share {
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CXD2880_TNRDMD_XTAL_SHARE_NONE,
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CXD2880_TNRDMD_XTAL_SHARE_EXTREF,
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CXD2880_TNRDMD_XTAL_SHARE_MASTER,
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CXD2880_TNRDMD_XTAL_SHARE_SLAVE
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};
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enum cxd2880_tnrdmd_spectrum_sense {
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CXD2880_TNRDMD_SPECTRUM_NORMAL,
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CXD2880_TNRDMD_SPECTRUM_INV
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};
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enum cxd2880_tnrdmd_cfg_id {
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CXD2880_TNRDMD_CFG_OUTPUT_SEL_MSB,
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CXD2880_TNRDMD_CFG_TSVALID_ACTIVE_HI,
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CXD2880_TNRDMD_CFG_TSSYNC_ACTIVE_HI,
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CXD2880_TNRDMD_CFG_TSERR_ACTIVE_HI,
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CXD2880_TNRDMD_CFG_LATCH_ON_POSEDGE,
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CXD2880_TNRDMD_CFG_TSCLK_CONT,
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CXD2880_TNRDMD_CFG_TSCLK_MASK,
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CXD2880_TNRDMD_CFG_TSVALID_MASK,
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CXD2880_TNRDMD_CFG_TSERR_MASK,
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CXD2880_TNRDMD_CFG_TSERR_VALID_DIS,
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CXD2880_TNRDMD_CFG_TSPIN_CURRENT,
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CXD2880_TNRDMD_CFG_TSPIN_PULLUP_MANUAL,
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CXD2880_TNRDMD_CFG_TSPIN_PULLUP,
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CXD2880_TNRDMD_CFG_TSCLK_FREQ,
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CXD2880_TNRDMD_CFG_TSBYTECLK_MANUAL,
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CXD2880_TNRDMD_CFG_TS_PACKET_GAP,
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CXD2880_TNRDMD_CFG_TS_BACKWARDS_COMPATIBLE,
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CXD2880_TNRDMD_CFG_PWM_VALUE,
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CXD2880_TNRDMD_CFG_INTERRUPT,
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CXD2880_TNRDMD_CFG_INTERRUPT_LOCK_SEL,
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CXD2880_TNRDMD_CFG_INTERRUPT_INV_LOCK_SEL,
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CXD2880_TNRDMD_CFG_TS_BUF_ALMOST_EMPTY_THRS,
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CXD2880_TNRDMD_CFG_TS_BUF_ALMOST_FULL_THRS,
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CXD2880_TNRDMD_CFG_TS_BUF_RRDY_THRS,
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CXD2880_TNRDMD_CFG_FIXED_CLOCKMODE,
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CXD2880_TNRDMD_CFG_CABLE_INPUT,
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CXD2880_TNRDMD_CFG_DVBT2_FEF_INTERMITTENT_BASE,
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CXD2880_TNRDMD_CFG_DVBT2_FEF_INTERMITTENT_LITE,
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CXD2880_TNRDMD_CFG_BLINDTUNE_DVBT2_FIRST,
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CXD2880_TNRDMD_CFG_DVBT_BERN_PERIOD,
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CXD2880_TNRDMD_CFG_DVBT_VBER_PERIOD,
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CXD2880_TNRDMD_CFG_DVBT_PER_MES,
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CXD2880_TNRDMD_CFG_DVBT2_BBER_MES,
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CXD2880_TNRDMD_CFG_DVBT2_LBER_MES,
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CXD2880_TNRDMD_CFG_DVBT2_PER_MES,
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};
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enum cxd2880_tnrdmd_lock_result {
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CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT,
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CXD2880_TNRDMD_LOCK_RESULT_LOCKED,
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CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED
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};
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enum cxd2880_tnrdmd_gpio_mode {
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CXD2880_TNRDMD_GPIO_MODE_OUTPUT = 0x00,
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CXD2880_TNRDMD_GPIO_MODE_INPUT = 0x01,
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CXD2880_TNRDMD_GPIO_MODE_INT = 0x02,
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CXD2880_TNRDMD_GPIO_MODE_FEC_FAIL = 0x03,
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CXD2880_TNRDMD_GPIO_MODE_PWM = 0x04,
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CXD2880_TNRDMD_GPIO_MODE_EWS = 0x05,
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CXD2880_TNRDMD_GPIO_MODE_EEW = 0x06
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};
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enum cxd2880_tnrdmd_serial_ts_clk {
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CXD2880_TNRDMD_SERIAL_TS_CLK_FULL,
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CXD2880_TNRDMD_SERIAL_TS_CLK_HALF
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};
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struct cxd2880_tnrdmd_cfg_mem {
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enum cxd2880_io_tgt tgt;
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u8 bank;
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u8 address;
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u8 value;
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u8 bit_mask;
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};
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struct cxd2880_tnrdmd_pid_cfg {
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u8 is_en;
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u16 pid;
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};
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struct cxd2880_tnrdmd_pid_ftr_cfg {
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u8 is_negative;
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struct cxd2880_tnrdmd_pid_cfg pid_cfg[32];
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};
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struct cxd2880_tnrdmd_lna_thrs {
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u8 off_on;
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u8 on_off;
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};
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struct cxd2880_tnrdmd_lna_thrs_tbl_air {
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struct cxd2880_tnrdmd_lna_thrs thrs[24];
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};
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struct cxd2880_tnrdmd_lna_thrs_tbl_cable {
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struct cxd2880_tnrdmd_lna_thrs thrs[32];
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};
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struct cxd2880_tnrdmd_create_param {
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enum cxd2880_tnrdmd_tsout_if ts_output_if;
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u8 en_internal_ldo;
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enum cxd2880_tnrdmd_xtal_share xtal_share_type;
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u8 xosc_cap;
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u8 xosc_i;
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u8 is_cxd2881gg;
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u8 stationary_use;
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};
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struct cxd2880_tnrdmd_diver_create_param {
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enum cxd2880_tnrdmd_tsout_if ts_output_if;
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u8 en_internal_ldo;
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u8 xosc_cap_main;
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u8 xosc_i_main;
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u8 xosc_i_sub;
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u8 is_cxd2881gg;
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u8 stationary_use;
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};
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struct cxd2880_tnrdmd {
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struct cxd2880_tnrdmd *diver_sub;
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struct cxd2880_io *io;
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struct cxd2880_tnrdmd_create_param create_param;
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enum cxd2880_tnrdmd_divermode diver_mode;
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enum cxd2880_tnrdmd_clockmode fixed_clk_mode;
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u8 is_cable_input;
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u8 en_fef_intmtnt_base;
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u8 en_fef_intmtnt_lite;
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u8 blind_tune_dvbt2_first;
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int (*rf_lvl_cmpstn)(struct cxd2880_tnrdmd *tnr_dmd,
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int *rf_lvl_db);
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struct cxd2880_tnrdmd_lna_thrs_tbl_air *lna_thrs_tbl_air;
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struct cxd2880_tnrdmd_lna_thrs_tbl_cable *lna_thrs_tbl_cable;
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u8 srl_ts_clk_mod_cnts;
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enum cxd2880_tnrdmd_serial_ts_clk srl_ts_clk_frq;
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u8 ts_byte_clk_manual_setting;
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u8 is_ts_backwards_compatible_mode;
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struct cxd2880_tnrdmd_cfg_mem cfg_mem[CXD2880_TNRDMD_MAX_CFG_MEM_COUNT];
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u8 cfg_mem_last_entry;
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struct cxd2880_tnrdmd_pid_ftr_cfg pid_ftr_cfg;
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u8 pid_ftr_cfg_en;
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void *user;
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enum cxd2880_tnrdmd_chip_id chip_id;
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enum cxd2880_tnrdmd_state state;
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enum cxd2880_tnrdmd_clockmode clk_mode;
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u32 frequency_khz;
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enum cxd2880_dtv_sys sys;
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enum cxd2880_dtv_bandwidth bandwidth;
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u8 scan_mode;
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atomic_t cancel;
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};
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int cxd2880_tnrdmd_create(struct cxd2880_tnrdmd *tnr_dmd,
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struct cxd2880_io *io,
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struct cxd2880_tnrdmd_create_param
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*create_param);
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int cxd2880_tnrdmd_diver_create(struct cxd2880_tnrdmd
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*tnr_dmd_main,
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struct cxd2880_io *io_main,
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struct cxd2880_tnrdmd *tnr_dmd_sub,
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struct cxd2880_io *io_sub,
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struct
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cxd2880_tnrdmd_diver_create_param
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*create_param);
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int cxd2880_tnrdmd_init1(struct cxd2880_tnrdmd *tnr_dmd);
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int cxd2880_tnrdmd_init2(struct cxd2880_tnrdmd *tnr_dmd);
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int cxd2880_tnrdmd_check_internal_cpu_status(struct cxd2880_tnrdmd
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*tnr_dmd,
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u8 *task_completed);
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int cxd2880_tnrdmd_common_tune_setting1(struct cxd2880_tnrdmd
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*tnr_dmd,
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enum cxd2880_dtv_sys sys,
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u32 frequency_khz,
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enum cxd2880_dtv_bandwidth
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bandwidth, u8 one_seg_opt,
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u8 one_seg_opt_shft_dir);
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int cxd2880_tnrdmd_common_tune_setting2(struct cxd2880_tnrdmd
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*tnr_dmd,
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enum cxd2880_dtv_sys sys,
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u8 en_fef_intmtnt_ctrl);
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int cxd2880_tnrdmd_sleep(struct cxd2880_tnrdmd *tnr_dmd);
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int cxd2880_tnrdmd_set_cfg(struct cxd2880_tnrdmd *tnr_dmd,
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enum cxd2880_tnrdmd_cfg_id id,
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int value);
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int cxd2880_tnrdmd_gpio_set_cfg(struct cxd2880_tnrdmd *tnr_dmd,
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u8 id,
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u8 en,
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enum cxd2880_tnrdmd_gpio_mode mode,
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u8 open_drain, u8 invert);
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int cxd2880_tnrdmd_gpio_set_cfg_sub(struct cxd2880_tnrdmd *tnr_dmd,
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u8 id,
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u8 en,
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enum cxd2880_tnrdmd_gpio_mode
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mode, u8 open_drain,
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u8 invert);
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int cxd2880_tnrdmd_gpio_read(struct cxd2880_tnrdmd *tnr_dmd,
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u8 id, u8 *value);
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int cxd2880_tnrdmd_gpio_read_sub(struct cxd2880_tnrdmd *tnr_dmd,
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u8 id, u8 *value);
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int cxd2880_tnrdmd_gpio_write(struct cxd2880_tnrdmd *tnr_dmd,
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u8 id, u8 value);
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int cxd2880_tnrdmd_gpio_write_sub(struct cxd2880_tnrdmd *tnr_dmd,
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u8 id, u8 value);
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int cxd2880_tnrdmd_interrupt_read(struct cxd2880_tnrdmd *tnr_dmd,
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u16 *value);
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int cxd2880_tnrdmd_interrupt_clear(struct cxd2880_tnrdmd *tnr_dmd,
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u16 value);
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int cxd2880_tnrdmd_ts_buf_clear(struct cxd2880_tnrdmd *tnr_dmd,
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u8 clear_overflow_flag,
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u8 clear_underflow_flag,
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u8 clear_buf);
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int cxd2880_tnrdmd_chip_id(struct cxd2880_tnrdmd *tnr_dmd,
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enum cxd2880_tnrdmd_chip_id *chip_id);
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int cxd2880_tnrdmd_set_and_save_reg_bits(struct cxd2880_tnrdmd
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*tnr_dmd,
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enum cxd2880_io_tgt tgt,
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u8 bank, u8 address,
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u8 value, u8 bit_mask);
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int cxd2880_tnrdmd_set_scan_mode(struct cxd2880_tnrdmd *tnr_dmd,
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enum cxd2880_dtv_sys sys,
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u8 scan_mode_end);
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int cxd2880_tnrdmd_set_pid_ftr(struct cxd2880_tnrdmd *tnr_dmd,
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struct cxd2880_tnrdmd_pid_ftr_cfg
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*pid_ftr_cfg);
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int cxd2880_tnrdmd_set_rf_lvl_cmpstn(struct cxd2880_tnrdmd
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*tnr_dmd,
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int (*rf_lvl_cmpstn)
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(struct cxd2880_tnrdmd *,
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int *));
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|
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int cxd2880_tnrdmd_set_rf_lvl_cmpstn_sub(struct cxd2880_tnrdmd *tnr_dmd,
|
||||
int (*rf_lvl_cmpstn)
|
||||
(struct cxd2880_tnrdmd *,
|
||||
int *));
|
||||
|
||||
int cxd2880_tnrdmd_set_lna_thrs(struct cxd2880_tnrdmd *tnr_dmd,
|
||||
struct
|
||||
cxd2880_tnrdmd_lna_thrs_tbl_air
|
||||
*tbl_air,
|
||||
struct
|
||||
cxd2880_tnrdmd_lna_thrs_tbl_cable
|
||||
*tbl_cable);
|
||||
|
||||
int cxd2880_tnrdmd_set_lna_thrs_sub(struct cxd2880_tnrdmd *tnr_dmd,
|
||||
struct
|
||||
cxd2880_tnrdmd_lna_thrs_tbl_air
|
||||
*tbl_air,
|
||||
struct
|
||||
cxd2880_tnrdmd_lna_thrs_tbl_cable
|
||||
*tbl_cable);
|
||||
|
||||
int cxd2880_tnrdmd_set_ts_pin_high_low(struct cxd2880_tnrdmd
|
||||
*tnr_dmd, u8 en, u8 value);
|
||||
|
||||
int cxd2880_tnrdmd_set_ts_output(struct cxd2880_tnrdmd *tnr_dmd,
|
||||
u8 en);
|
||||
|
||||
int slvt_freeze_reg(struct cxd2880_tnrdmd *tnr_dmd);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* cxd2880_tnrdmd_driver_version.h
|
||||
* Sony CXD2880 DVB-T2/T tuner + demodulator driver
|
||||
* version information
|
||||
*
|
||||
* Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation
|
||||
*/
|
||||
|
||||
#define CXD2880_TNRDMD_DRIVER_VERSION "1.4.1 - 1.0.4"
|
||||
|
||||
#define CXD2880_TNRDMD_DRIVER_RELEASE_DATE "2018-01-17"
|
||||
|
|
@ -0,0 +1,150 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* cxd2880_tnrdmd_mon.c
|
||||
* Sony CXD2880 DVB-T2/T tuner + demodulator driver
|
||||
* common monitor functions
|
||||
*
|
||||
* Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation
|
||||
*/
|
||||
|
||||
#include "cxd2880_common.h"
|
||||
#include "cxd2880_tnrdmd_mon.h"
|
||||
|
||||
static const u8 rf_lvl_seq[2] = {
|
||||
0x80, 0x00,
|
||||
};
|
||||
|
||||
int cxd2880_tnrdmd_mon_rf_lvl(struct cxd2880_tnrdmd *tnr_dmd,
|
||||
int *rf_lvl_db)
|
||||
{
|
||||
u8 rdata[2];
|
||||
int ret;
|
||||
|
||||
if (!tnr_dmd || !rf_lvl_db)
|
||||
return -EINVAL;
|
||||
|
||||
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
|
||||
return -EINVAL;
|
||||
|
||||
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
|
||||
CXD2880_IO_TGT_DMD,
|
||||
0x00, 0x00);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
|
||||
CXD2880_IO_TGT_DMD,
|
||||
0x10, 0x01);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
|
||||
CXD2880_IO_TGT_SYS,
|
||||
0x00, 0x10);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = tnr_dmd->io->write_regs(tnr_dmd->io,
|
||||
CXD2880_IO_TGT_SYS,
|
||||
0x5b, rf_lvl_seq, 2);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
usleep_range(2000, 3000);
|
||||
|
||||
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
|
||||
CXD2880_IO_TGT_SYS,
|
||||
0x00, 0x1a);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
|
||||
CXD2880_IO_TGT_SYS,
|
||||
0x15, rdata, 2);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (rdata[0] || rdata[1])
|
||||
return -EINVAL;
|
||||
|
||||
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
|
||||
CXD2880_IO_TGT_SYS,
|
||||
0x11, rdata, 2);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
*rf_lvl_db =
|
||||
cxd2880_convert2s_complement((rdata[0] << 3) |
|
||||
((rdata[1] & 0xe0) >> 5), 11);
|
||||
|
||||
*rf_lvl_db *= 125;
|
||||
|
||||
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
|
||||
CXD2880_IO_TGT_DMD,
|
||||
0x00, 0x00);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
|
||||
CXD2880_IO_TGT_DMD,
|
||||
0x10, 0x00);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (tnr_dmd->rf_lvl_cmpstn)
|
||||
ret = tnr_dmd->rf_lvl_cmpstn(tnr_dmd, rf_lvl_db);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int cxd2880_tnrdmd_mon_rf_lvl_sub(struct cxd2880_tnrdmd *tnr_dmd,
|
||||
int *rf_lvl_db)
|
||||
{
|
||||
if (!tnr_dmd || !rf_lvl_db)
|
||||
return -EINVAL;
|
||||
|
||||
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
|
||||
return -EINVAL;
|
||||
|
||||
return cxd2880_tnrdmd_mon_rf_lvl(tnr_dmd->diver_sub, rf_lvl_db);
|
||||
}
|
||||
|
||||
int cxd2880_tnrdmd_mon_internal_cpu_status(struct cxd2880_tnrdmd
|
||||
*tnr_dmd, u16 *status)
|
||||
{
|
||||
u8 data[2] = { 0 };
|
||||
int ret;
|
||||
|
||||
if (!tnr_dmd || !status)
|
||||
return -EINVAL;
|
||||
|
||||
ret = tnr_dmd->io->write_reg(tnr_dmd->io,
|
||||
CXD2880_IO_TGT_SYS,
|
||||
0x00, 0x1a);
|
||||
if (ret)
|
||||
return ret;
|
||||
ret = tnr_dmd->io->read_regs(tnr_dmd->io,
|
||||
CXD2880_IO_TGT_SYS,
|
||||
0x15, data, 2);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
*status = (data[0] << 8) | data[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int cxd2880_tnrdmd_mon_internal_cpu_status_sub(struct
|
||||
cxd2880_tnrdmd
|
||||
*tnr_dmd,
|
||||
u16 *status)
|
||||
{
|
||||
if (!tnr_dmd || !status)
|
||||
return -EINVAL;
|
||||
|
||||
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN)
|
||||
return -EINVAL;
|
||||
|
||||
return cxd2880_tnrdmd_mon_internal_cpu_status(tnr_dmd->diver_sub,
|
||||
status);
|
||||
}
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* cxd2880_tnrdmd_mon.h
|
||||
* Sony CXD2880 DVB-T2/T tuner + demodulator driver
|
||||
* common monitor interface
|
||||
*
|
||||
* Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation
|
||||
*/
|
||||
|
||||
#ifndef CXD2880_TNRDMD_MON_H
|
||||
#define CXD2880_TNRDMD_MON_H
|
||||
|
||||
#include "cxd2880_common.h"
|
||||
#include "cxd2880_tnrdmd.h"
|
||||
|
||||
int cxd2880_tnrdmd_mon_rf_lvl(struct cxd2880_tnrdmd *tnr_dmd,
|
||||
int *rf_lvl_db);
|
||||
|
||||
int cxd2880_tnrdmd_mon_rf_lvl_sub(struct cxd2880_tnrdmd *tnr_dmd,
|
||||
int *rf_lvl_db);
|
||||
|
||||
int cxd2880_tnrdmd_mon_internal_cpu_status(struct cxd2880_tnrdmd
|
||||
*tnr_dmd, u16 *status);
|
||||
|
||||
int cxd2880_tnrdmd_mon_internal_cpu_status_sub(struct
|
||||
cxd2880_tnrdmd
|
||||
*tnr_dmd,
|
||||
u16 *status);
|
||||
#endif
|
||||
Loading…
Reference in New Issue