cxgb4: Added support in debugfs to dump cim ingress bound queue contents
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Hariprasad Shenai
David S. Miller
parent
dc9daab226
commit
e5f0e43bee
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@ -1054,6 +1054,8 @@ int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
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u64 *parity);
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int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
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u64 *parity);
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int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
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size_t n);
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int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
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unsigned int *valp);
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int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
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@ -239,6 +239,42 @@ static const struct file_operations cim_qcfg_fops = {
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.release = single_release,
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};
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static int cimq_show(struct seq_file *seq, void *v, int idx)
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{
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const u32 *p = v;
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seq_printf(seq, "%#06x: %08x %08x %08x %08x\n", idx * 16, p[0], p[1],
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p[2], p[3]);
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return 0;
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}
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static int cim_ibq_open(struct inode *inode, struct file *file)
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{
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int ret;
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struct seq_tab *p;
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unsigned int qid = (uintptr_t)inode->i_private & 7;
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struct adapter *adap = inode->i_private - qid;
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p = seq_open_tab(file, CIM_IBQ_SIZE, 4 * sizeof(u32), 0, cimq_show);
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if (!p)
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return -ENOMEM;
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ret = t4_read_cim_ibq(adap, qid, (u32 *)p->data, CIM_IBQ_SIZE * 4);
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if (ret < 0)
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seq_release_private(inode, file);
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else
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ret = 0;
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return ret;
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}
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static const struct file_operations cim_ibq_fops = {
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.owner = THIS_MODULE,
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.open = cim_ibq_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = seq_release_private
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};
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/* Firmware Device Log dump. */
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static const char * const devlog_level_strings[] = {
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[FW_DEVLOG_LEVEL_EMERG] = "EMERG",
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@ -1346,6 +1382,12 @@ int t4_setup_debugfs(struct adapter *adap)
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{ "rss_pf_config", &rss_pf_config_debugfs_fops, S_IRUSR, 0 },
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{ "rss_vf_config", &rss_vf_config_debugfs_fops, S_IRUSR, 0 },
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{ "sge_qinfo", &sge_qinfo_debugfs_fops, S_IRUSR, 0 },
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{ "ibq_tp0", &cim_ibq_fops, S_IRUSR, 0 },
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{ "ibq_tp1", &cim_ibq_fops, S_IRUSR, 1 },
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{ "ibq_ulp", &cim_ibq_fops, S_IRUSR, 2 },
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{ "ibq_sge0", &cim_ibq_fops, S_IRUSR, 3 },
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{ "ibq_sge1", &cim_ibq_fops, S_IRUSR, 4 },
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{ "ibq_ncsi", &cim_ibq_fops, S_IRUSR, 5 },
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#if IS_ENABLED(CONFIG_IPV6)
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{ "clip_tbl", &clip_tbl_debugfs_fops, S_IRUSR, 0 },
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#endif
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@ -4525,6 +4525,48 @@ void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
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}
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}
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/**
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* t4_read_cim_ibq - read the contents of a CIM inbound queue
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* @adap: the adapter
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* @qid: the queue index
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* @data: where to store the queue contents
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* @n: capacity of @data in 32-bit words
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*
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* Reads the contents of the selected CIM queue starting at address 0 up
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* to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
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* error and the number of 32-bit words actually read on success.
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*/
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int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
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{
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int i, err, attempts;
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unsigned int addr;
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const unsigned int nwords = CIM_IBQ_SIZE * 4;
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if (qid > 5 || (n & 3))
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return -EINVAL;
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addr = qid * nwords;
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if (n > nwords)
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n = nwords;
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/* It might take 3-10ms before the IBQ debug read access is allowed.
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* Wait for 1 Sec with a delay of 1 usec.
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*/
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attempts = 1000000;
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for (i = 0; i < n; i++, addr++) {
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t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
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IBQDBGEN_F);
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err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
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attempts, 1);
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if (err)
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return err;
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*data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
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}
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t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
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return i;
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}
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/**
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* t4_cim_read - read a block from CIM internal address space
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* @adap: the adapter
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@ -60,6 +60,7 @@ enum {
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CIM_NUM_OBQ = 6, /* # of CIM OBQs */
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CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */
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CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */
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CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */
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};
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enum {
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@ -2538,6 +2538,23 @@
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#define HOSTWRITE_V(x) ((x) << HOSTWRITE_S)
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#define HOSTWRITE_F HOSTWRITE_V(1U)
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#define CIM_IBQ_DBG_CFG_A 0x7b60
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#define IBQDBGADDR_S 16
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#define IBQDBGADDR_M 0xfffU
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#define IBQDBGADDR_V(x) ((x) << IBQDBGADDR_S)
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#define IBQDBGADDR_G(x) (((x) >> IBQDBGADDR_S) & IBQDBGADDR_M)
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#define IBQDBGBUSY_S 1
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#define IBQDBGBUSY_V(x) ((x) << IBQDBGBUSY_S)
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#define IBQDBGBUSY_F IBQDBGBUSY_V(1U)
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#define IBQDBGEN_S 0
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#define IBQDBGEN_V(x) ((x) << IBQDBGEN_S)
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#define IBQDBGEN_F IBQDBGEN_V(1U)
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#define CIM_IBQ_DBG_DATA_A 0x7b68
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#define UPDBGLARDEN_S 1
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#define UPDBGLARDEN_V(x) ((x) << UPDBGLARDEN_S)
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#define UPDBGLARDEN_F UPDBGLARDEN_V(1U)
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