ARC: clocksource: DT based probe
- Remove explicit clocksource setup and let it be done by OF framework
by defining CLOCKSOURCE_OF_DECLARE() for various timers
- This allows multiple clocksources to be potentially registered
simultaneouly: previously we could only do one - as all of them had
same arc_counter_setup() routine for registration
- Setup routines also ensure that the underlying timer actually exists.
- Remove some of the panic() calls if underlying timer is NOT detected as
fallback clocksource might still be available
1. If GRFC doesn't exist, jiffies clocksource gets registered anyways
2. if RTC doesn't exist, TIMER1 can take over (as it is always
present)
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta
parent
77c8d0d6b3
commit
e608b53ea8
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@ -116,15 +116,13 @@ static void mcip_probe_n_setup(void)
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IS_AVAIL1(mp.dbg, "DEBUG "),
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IS_AVAIL1(mp.gfrc, "GFRC"));
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cpuinfo_arc700[0].extn.gfrc = mp.gfrc;
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idu_detected = mp.idu;
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if (mp.dbg) {
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__mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf);
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__mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf);
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}
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if (IS_ENABLED(CONFIG_ARC_HAS_GFRC) && !mp.gfrc)
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panic("kernel trying to use non-existent GFRC\n");
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}
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struct plat_smp_ops plat_smp_ops = {
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@ -313,9 +313,6 @@ static void arc_chk_core_config(void)
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if (!cpu->extn.timer1)
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panic("Timer1 is not present!\n");
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if (IS_ENABLED(CONFIG_ARC_HAS_RTC) && !cpu->extn.rtc)
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panic("RTC is not present\n");
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#ifdef CONFIG_ARC_HAS_DCCM
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/*
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* DCCM can be arbit placed in hardware.
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@ -83,12 +83,7 @@ static int noinline arc_get_timer_clk(struct device_node *node)
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#ifdef CONFIG_ARC_HAS_GFRC
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static int arc_counter_setup(void)
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{
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return 1;
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}
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static cycle_t arc_counter_read(struct clocksource *cs)
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static cycle_t arc_read_gfrc(struct clocksource *cs)
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{
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unsigned long flags;
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union {
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@ -113,15 +108,31 @@ static cycle_t arc_counter_read(struct clocksource *cs)
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return stamp.full;
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}
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static struct clocksource arc_counter = {
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static struct clocksource arc_counter_gfrc = {
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.name = "ARConnect GFRC",
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.rating = 400,
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.read = arc_counter_read,
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.read = arc_read_gfrc,
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.mask = CLOCKSOURCE_MASK(64),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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#else
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static void __init arc_cs_setup_gfrc(struct device_node *node)
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{
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int exists = cpuinfo_arc700[0].extn.gfrc;
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int ret;
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if (WARN(!exists, "Global-64-bit-Ctr clocksource not detected"))
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return;
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ret = arc_get_timer_clk(node);
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if (ret)
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return;
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clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq);
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}
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CLOCKSOURCE_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc);
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#endif
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#ifdef CONFIG_ARC_HAS_RTC
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@ -129,15 +140,7 @@ static struct clocksource arc_counter = {
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#define AUX_RTC_LOW 0x104
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#define AUX_RTC_HIGH 0x105
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int arc_counter_setup(void)
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{
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write_aux_reg(AUX_RTC_CTRL, 1);
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/* Not usable in SMP */
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return !IS_ENABLED(CONFIG_SMP);
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}
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static cycle_t arc_counter_read(struct clocksource *cs)
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static cycle_t arc_read_rtc(struct clocksource *cs)
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{
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unsigned long status;
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union {
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@ -161,44 +164,73 @@ static cycle_t arc_counter_read(struct clocksource *cs)
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return stamp.full;
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}
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static struct clocksource arc_counter = {
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static struct clocksource arc_counter_rtc = {
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.name = "ARCv2 RTC",
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.rating = 350,
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.read = arc_counter_read,
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.read = arc_read_rtc,
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.mask = CLOCKSOURCE_MASK(64),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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#else /* !CONFIG_ARC_HAS_RTC */
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static void __init arc_cs_setup_rtc(struct device_node *node)
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{
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int exists = cpuinfo_arc700[smp_processor_id()].extn.rtc;
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int ret;
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if (WARN(!exists, "Local-64-bit-Ctr clocksource not detected"))
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return;
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/* Local to CPU hence not usable in SMP */
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if (WARN(IS_ENABLED(CONFIG_SMP), "Local-64-bit-Ctr not usable in SMP"))
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return;
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ret = arc_get_timer_clk(node);
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if (ret)
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return;
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write_aux_reg(AUX_RTC_CTRL, 1);
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clocksource_register_hz(&arc_counter_rtc, arc_timer_freq);
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}
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CLOCKSOURCE_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc);
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#endif
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/*
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* set 32bit TIMER1 to keep counting monotonically and wraparound
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* 32bit TIMER1 to keep counting monotonically and wraparound
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*/
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int arc_counter_setup(void)
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{
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write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX);
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write_aux_reg(ARC_REG_TIMER1_CNT, 0);
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write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
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/* Not usable in SMP */
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return !IS_ENABLED(CONFIG_SMP);
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}
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static cycle_t arc_counter_read(struct clocksource *cs)
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static cycle_t arc_read_timer1(struct clocksource *cs)
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{
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return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT);
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}
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static struct clocksource arc_counter = {
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static struct clocksource arc_counter_timer1 = {
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.name = "ARC Timer1",
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.rating = 300,
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.read = arc_counter_read,
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.read = arc_read_timer1,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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#endif
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#endif
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static void __init arc_cs_setup_timer1(struct device_node *node)
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{
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int ret;
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/* Local to CPU hence not usable in SMP */
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if (IS_ENABLED(CONFIG_SMP))
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return;
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ret = arc_get_timer_clk(node);
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if (ret)
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return;
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write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX);
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write_aux_reg(ARC_REG_TIMER1_CNT, 0);
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write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
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clocksource_register_hz(&arc_counter_timer1, arc_timer_freq);
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}
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/********** Clock Event Device *********/
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@ -320,29 +352,25 @@ static void __init arc_clockevent_setup(struct device_node *node)
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enable_percpu_irq(arc_timer_irq, 0);
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}
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CLOCKSOURCE_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_clockevent_setup);
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static void __init arc_of_timer_init(struct device_node *np)
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{
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static int init_count = 0;
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if (!init_count) {
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init_count = 1;
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arc_clockevent_setup(np);
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} else {
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arc_cs_setup_timer1(np);
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}
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}
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CLOCKSOURCE_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init);
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/*
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* Called from start_kernel() - boot CPU only
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*
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* -Sets up h/w timers as applicable on boot cpu
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* -Also sets up any global state needed for timer subsystem:
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* - for "counting" timer, registers a clocksource, usable across CPUs
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* (provided that underlying counter h/w is synchronized across cores)
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*/
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void __init time_init(void)
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{
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of_clk_init(NULL);
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clocksource_probe();
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/*
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* sets up the timekeeping free-flowing counter which also returns
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* whether the counter is usable as clocksource
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*/
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if (arc_counter_setup())
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/*
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* CLK upto 4.29 GHz can be safely represented in 32 bits
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* because Max 32 bit number is 4,294,967,295
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*/
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clocksource_register_hz(&arc_counter, arc_timer_freq);
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}
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