ath10k: Add support for htt_data_tx_desc_64 descriptor
WCN3990 target uses 64 bit frags_paddr in htt tx descriptor, which holds the physical address of SKB fragments in tx data path. In order to support 64 bit bit frags_paddr in htt tx descriptor, define htt_data_tx_desc_64 descriptor and ath10k_htt_tx_64 method for handling tx data path with new descriptor fields. Signed-off-by: Govind Singh <govinds@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
This commit is contained in:
Govind Singh
Kalle Valo
parent
71ad709610
commit
e62ee5c381
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@ -187,6 +187,22 @@ struct htt_data_tx_desc {
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u8 prefetch[0]; /* start of frame, for FW classification engine */
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} __packed;
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struct htt_data_tx_desc_64 {
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u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */
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__le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */
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__le16 len;
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__le16 id;
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__le64 frags_paddr;
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union {
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__le32 peerid;
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struct {
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__le16 peerid;
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__le16 freq;
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} __packed offchan_tx;
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} __packed;
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u8 prefetch[0]; /* start of frame, for FW classification engine */
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} __packed;
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enum htt_rx_ring_flags {
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HTT_RX_RING_FLAGS_MAC80211_HDR = 1 << 0,
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HTT_RX_RING_FLAGS_MSDU_PAYLOAD = 1 << 1,
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@ -1648,13 +1664,20 @@ struct htt_peer_unmap_event {
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u16 peer_id;
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};
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struct ath10k_htt_txbuf {
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struct ath10k_htt_txbuf_32 {
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struct htt_data_tx_desc_frag frags[2];
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struct ath10k_htc_hdr htc_hdr;
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struct htt_cmd_hdr cmd_hdr;
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struct htt_data_tx_desc cmd_tx;
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} __packed;
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struct ath10k_htt_txbuf_64 {
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struct htt_data_tx_desc_frag frags[2];
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struct ath10k_htc_hdr htc_hdr;
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struct htt_cmd_hdr cmd_hdr;
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struct htt_data_tx_desc_64 cmd_tx;
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} __packed;
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struct ath10k_htt {
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struct ath10k *ar;
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enum ath10k_htc_ep_id eid;
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@ -1785,7 +1808,11 @@ struct ath10k_htt {
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struct {
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dma_addr_t paddr;
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struct ath10k_htt_txbuf *vaddr;
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union {
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struct ath10k_htt_txbuf_32 *vaddr_txbuff_32;
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struct ath10k_htt_txbuf_64 *vaddr_txbuff_64;
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};
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size_t size;
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} txbuf;
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struct {
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@ -1808,6 +1835,10 @@ struct ath10k_htt_tx_ops {
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int (*htt_send_frag_desc_bank_cfg)(struct ath10k_htt *htt);
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int (*htt_alloc_frag_desc)(struct ath10k_htt *htt);
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void (*htt_free_frag_desc)(struct ath10k_htt *htt);
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int (*htt_tx)(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode,
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struct sk_buff *msdu);
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int (*htt_alloc_txbuff)(struct ath10k_htt *htt);
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void (*htt_free_txbuff)(struct ath10k_htt *htt);
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};
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#define RX_HTT_HDR_STATUS_LEN 64
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@ -1912,9 +1943,6 @@ int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt,
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int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb);
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void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id);
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int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu);
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int ath10k_htt_tx(struct ath10k_htt *htt,
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enum ath10k_hw_txrx_mode txmode,
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struct sk_buff *msdu);
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void ath10k_htt_rx_pktlog_completion_handler(struct ath10k *ar,
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struct sk_buff *skb);
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int ath10k_htt_txrx_compl_task(struct ath10k *ar, int budget);
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@ -229,30 +229,69 @@ void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id)
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idr_remove(&htt->pending_tx, msdu_id);
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}
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static void ath10k_htt_tx_free_cont_txbuf(struct ath10k_htt *htt)
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static void ath10k_htt_tx_free_cont_txbuf_32(struct ath10k_htt *htt)
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{
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struct ath10k *ar = htt->ar;
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size_t size;
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if (!htt->txbuf.vaddr)
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if (!htt->txbuf.vaddr_txbuff_32)
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return;
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size = htt->max_num_pending_tx * sizeof(struct ath10k_htt_txbuf);
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dma_free_coherent(ar->dev, size, htt->txbuf.vaddr, htt->txbuf.paddr);
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htt->txbuf.vaddr = NULL;
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size = htt->txbuf.size;
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dma_free_coherent(ar->dev, size, htt->txbuf.vaddr_txbuff_32,
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htt->txbuf.paddr);
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htt->txbuf.vaddr_txbuff_32 = NULL;
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}
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static int ath10k_htt_tx_alloc_cont_txbuf(struct ath10k_htt *htt)
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static int ath10k_htt_tx_alloc_cont_txbuf_32(struct ath10k_htt *htt)
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{
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struct ath10k *ar = htt->ar;
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size_t size;
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size = htt->max_num_pending_tx * sizeof(struct ath10k_htt_txbuf);
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htt->txbuf.vaddr = dma_alloc_coherent(ar->dev, size, &htt->txbuf.paddr,
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GFP_KERNEL);
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if (!htt->txbuf.vaddr)
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size = htt->max_num_pending_tx *
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sizeof(struct ath10k_htt_txbuf_32);
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htt->txbuf.vaddr_txbuff_32 = dma_alloc_coherent(ar->dev, size,
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&htt->txbuf.paddr,
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GFP_KERNEL);
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if (!htt->txbuf.vaddr_txbuff_32)
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return -ENOMEM;
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htt->txbuf.size = size;
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return 0;
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}
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static void ath10k_htt_tx_free_cont_txbuf_64(struct ath10k_htt *htt)
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{
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struct ath10k *ar = htt->ar;
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size_t size;
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if (!htt->txbuf.vaddr_txbuff_64)
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return;
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size = htt->txbuf.size;
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dma_free_coherent(ar->dev, size, htt->txbuf.vaddr_txbuff_64,
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htt->txbuf.paddr);
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htt->txbuf.vaddr_txbuff_64 = NULL;
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}
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static int ath10k_htt_tx_alloc_cont_txbuf_64(struct ath10k_htt *htt)
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{
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struct ath10k *ar = htt->ar;
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size_t size;
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size = htt->max_num_pending_tx *
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sizeof(struct ath10k_htt_txbuf_64);
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htt->txbuf.vaddr_txbuff_64 = dma_alloc_coherent(ar->dev, size,
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&htt->txbuf.paddr,
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GFP_KERNEL);
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if (!htt->txbuf.vaddr_txbuff_64)
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return -ENOMEM;
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htt->txbuf.size = size;
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return 0;
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}
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@ -404,7 +443,7 @@ static int ath10k_htt_tx_alloc_buf(struct ath10k_htt *htt)
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struct ath10k *ar = htt->ar;
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int ret;
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ret = ath10k_htt_tx_alloc_cont_txbuf(htt);
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ret = htt->tx_ops->htt_alloc_txbuff(htt);
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if (ret) {
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ath10k_err(ar, "failed to alloc cont tx buffer: %d\n", ret);
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return ret;
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@ -437,7 +476,7 @@ static int ath10k_htt_tx_alloc_buf(struct ath10k_htt *htt)
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htt->tx_ops->htt_free_frag_desc(htt);
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free_txbuf:
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ath10k_htt_tx_free_cont_txbuf(htt);
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htt->tx_ops->htt_free_txbuff(htt);
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return ret;
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}
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@ -491,7 +530,7 @@ void ath10k_htt_tx_destroy(struct ath10k_htt *htt)
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if (!htt->tx_mem_allocated)
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return;
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ath10k_htt_tx_free_cont_txbuf(htt);
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htt->tx_ops->htt_free_txbuff(htt);
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ath10k_htt_tx_free_txq(htt);
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htt->tx_ops->htt_free_frag_desc(htt);
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ath10k_htt_tx_free_txdone_fifo(htt);
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@ -1097,8 +1136,9 @@ int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
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return res;
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}
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int ath10k_htt_tx(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode,
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struct sk_buff *msdu)
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static int ath10k_htt_tx_32(struct ath10k_htt *htt,
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enum ath10k_hw_txrx_mode txmode,
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struct sk_buff *msdu)
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{
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struct ath10k *ar = htt->ar;
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struct device *dev = ar->dev;
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@ -1106,7 +1146,7 @@ int ath10k_htt_tx(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode,
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struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu);
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struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
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struct ath10k_hif_sg_item sg_items[2];
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struct ath10k_htt_txbuf *txbuf;
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struct ath10k_htt_txbuf_32 *txbuf;
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struct htt_data_tx_desc_frag *frags;
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bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET);
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u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu);
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@ -1132,9 +1172,9 @@ int ath10k_htt_tx(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode,
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prefetch_len = min(htt->prefetch_len, msdu->len);
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prefetch_len = roundup(prefetch_len, 4);
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txbuf = &htt->txbuf.vaddr[msdu_id];
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txbuf = htt->txbuf.vaddr_txbuff_32 + msdu_id;
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txbuf_paddr = htt->txbuf.paddr +
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(sizeof(struct ath10k_htt_txbuf) * msdu_id);
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(sizeof(struct ath10k_htt_txbuf_32) * msdu_id);
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if ((ieee80211_is_action(hdr->frame_control) ||
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ieee80211_is_deauth(hdr->frame_control) ||
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@ -1259,9 +1299,215 @@ int ath10k_htt_tx(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode,
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trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid);
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ath10k_dbg(ar, ATH10K_DBG_HTT,
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"htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %08x, msdu_paddr %08x vdev %hhu tid %hhu freq %hu\n",
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flags0, flags1, msdu->len, msdu_id, frags_paddr,
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(u32)skb_cb->paddr, vdev_id, tid, freq);
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"htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %pad, msdu_paddr %pad vdev %hhu tid %hhu freq %hu\n",
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flags0, flags1, msdu->len, msdu_id, &frags_paddr,
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&skb_cb->paddr, vdev_id, tid, freq);
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ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ",
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msdu->data, msdu->len);
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trace_ath10k_tx_hdr(ar, msdu->data, msdu->len);
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trace_ath10k_tx_payload(ar, msdu->data, msdu->len);
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sg_items[0].transfer_id = 0;
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sg_items[0].transfer_context = NULL;
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sg_items[0].vaddr = &txbuf->htc_hdr;
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sg_items[0].paddr = txbuf_paddr +
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sizeof(txbuf->frags);
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sg_items[0].len = sizeof(txbuf->htc_hdr) +
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sizeof(txbuf->cmd_hdr) +
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sizeof(txbuf->cmd_tx);
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sg_items[1].transfer_id = 0;
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sg_items[1].transfer_context = NULL;
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sg_items[1].vaddr = msdu->data;
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sg_items[1].paddr = skb_cb->paddr;
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sg_items[1].len = prefetch_len;
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res = ath10k_hif_tx_sg(htt->ar,
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htt->ar->htc.endpoint[htt->eid].ul_pipe_id,
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sg_items, ARRAY_SIZE(sg_items));
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if (res)
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goto err_unmap_msdu;
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return 0;
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err_unmap_msdu:
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dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
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err_free_msdu_id:
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ath10k_htt_tx_free_msdu_id(htt, msdu_id);
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err:
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return res;
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}
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static int ath10k_htt_tx_64(struct ath10k_htt *htt,
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enum ath10k_hw_txrx_mode txmode,
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struct sk_buff *msdu)
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{
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struct ath10k *ar = htt->ar;
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struct device *dev = ar->dev;
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struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data;
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struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu);
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struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
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struct ath10k_hif_sg_item sg_items[2];
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struct ath10k_htt_txbuf_64 *txbuf;
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struct htt_data_tx_desc_frag *frags;
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bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET);
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u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu);
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u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth);
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int prefetch_len;
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int res;
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u8 flags0 = 0;
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u16 msdu_id, flags1 = 0;
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u16 freq = 0;
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dma_addr_t frags_paddr = 0;
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u32 txbuf_paddr;
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struct htt_msdu_ext_desc_64 *ext_desc = NULL;
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struct htt_msdu_ext_desc_64 *ext_desc_t = NULL;
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spin_lock_bh(&htt->tx_lock);
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res = ath10k_htt_tx_alloc_msdu_id(htt, msdu);
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spin_unlock_bh(&htt->tx_lock);
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if (res < 0)
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goto err;
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msdu_id = res;
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prefetch_len = min(htt->prefetch_len, msdu->len);
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prefetch_len = roundup(prefetch_len, 4);
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txbuf = htt->txbuf.vaddr_txbuff_64 + msdu_id;
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txbuf_paddr = htt->txbuf.paddr +
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(sizeof(struct ath10k_htt_txbuf_64) * msdu_id);
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if ((ieee80211_is_action(hdr->frame_control) ||
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ieee80211_is_deauth(hdr->frame_control) ||
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ieee80211_is_disassoc(hdr->frame_control)) &&
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ieee80211_has_protected(hdr->frame_control)) {
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skb_put(msdu, IEEE80211_CCMP_MIC_LEN);
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} else if (!(skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) &&
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txmode == ATH10K_HW_TXRX_RAW &&
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ieee80211_has_protected(hdr->frame_control)) {
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skb_put(msdu, IEEE80211_CCMP_MIC_LEN);
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}
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skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
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DMA_TO_DEVICE);
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res = dma_mapping_error(dev, skb_cb->paddr);
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if (res) {
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res = -EIO;
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goto err_free_msdu_id;
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}
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if (unlikely(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN))
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freq = ar->scan.roc_freq;
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switch (txmode) {
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case ATH10K_HW_TXRX_RAW:
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case ATH10K_HW_TXRX_NATIVE_WIFI:
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flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
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/* pass through */
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case ATH10K_HW_TXRX_ETHERNET:
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if (ar->hw_params.continuous_frag_desc) {
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ext_desc_t = htt->frag_desc.vaddr_desc_64;
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memset(&ext_desc_t[msdu_id], 0,
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sizeof(struct htt_msdu_ext_desc_64));
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frags = (struct htt_data_tx_desc_frag *)
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&ext_desc_t[msdu_id].frags;
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ext_desc = &ext_desc_t[msdu_id];
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frags[0].tword_addr.paddr_lo =
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__cpu_to_le32(skb_cb->paddr);
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frags[0].tword_addr.paddr_hi =
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__cpu_to_le16(upper_32_bits(skb_cb->paddr));
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frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len);
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frags_paddr = htt->frag_desc.paddr +
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(sizeof(struct htt_msdu_ext_desc_64) * msdu_id);
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} else {
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frags = txbuf->frags;
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frags[0].tword_addr.paddr_lo =
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__cpu_to_le32(skb_cb->paddr);
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frags[0].tword_addr.paddr_hi =
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__cpu_to_le16(upper_32_bits(skb_cb->paddr));
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frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len);
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frags[1].tword_addr.paddr_lo = 0;
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frags[1].tword_addr.paddr_hi = 0;
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frags[1].tword_addr.len_16 = 0;
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}
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flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
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break;
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case ATH10K_HW_TXRX_MGMT:
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flags0 |= SM(ATH10K_HW_TXRX_MGMT,
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HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
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flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
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frags_paddr = skb_cb->paddr;
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break;
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}
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/* Normally all commands go through HTC which manages tx credits for
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* each endpoint and notifies when tx is completed.
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*
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* HTT endpoint is creditless so there's no need to care about HTC
|
||||
* flags. In that case it is trivial to fill the HTC header here.
|
||||
*
|
||||
* MSDU transmission is considered completed upon HTT event. This
|
||||
* implies no relevant resources can be freed until after the event is
|
||||
* received. That's why HTC tx completion handler itself is ignored by
|
||||
* setting NULL to transfer_context for all sg items.
|
||||
*
|
||||
* There is simply no point in pushing HTT TX_FRM through HTC tx path
|
||||
* as it's a waste of resources. By bypassing HTC it is possible to
|
||||
* avoid extra memory allocations, compress data structures and thus
|
||||
* improve performance.
|
||||
*/
|
||||
|
||||
txbuf->htc_hdr.eid = htt->eid;
|
||||
txbuf->htc_hdr.len = __cpu_to_le16(sizeof(txbuf->cmd_hdr) +
|
||||
sizeof(txbuf->cmd_tx) +
|
||||
prefetch_len);
|
||||
txbuf->htc_hdr.flags = 0;
|
||||
|
||||
if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT)
|
||||
flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT;
|
||||
|
||||
flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID);
|
||||
flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID);
|
||||
if (msdu->ip_summed == CHECKSUM_PARTIAL &&
|
||||
!test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
|
||||
flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD;
|
||||
flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD;
|
||||
if (ar->hw_params.continuous_frag_desc)
|
||||
ext_desc->flags |= HTT_MSDU_CHECKSUM_ENABLE;
|
||||
}
|
||||
|
||||
/* Prevent firmware from sending up tx inspection requests. There's
|
||||
* nothing ath10k can do with frames requested for inspection so force
|
||||
* it to simply rely a regular tx completion with discard status.
|
||||
*/
|
||||
flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED;
|
||||
|
||||
txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM;
|
||||
txbuf->cmd_tx.flags0 = flags0;
|
||||
txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1);
|
||||
txbuf->cmd_tx.len = __cpu_to_le16(msdu->len);
|
||||
txbuf->cmd_tx.id = __cpu_to_le16(msdu_id);
|
||||
|
||||
/* fill fragment descriptor */
|
||||
txbuf->cmd_tx.frags_paddr = __cpu_to_le64(frags_paddr);
|
||||
if (ath10k_mac_tx_frm_has_freq(ar)) {
|
||||
txbuf->cmd_tx.offchan_tx.peerid =
|
||||
__cpu_to_le16(HTT_INVALID_PEERID);
|
||||
txbuf->cmd_tx.offchan_tx.freq =
|
||||
__cpu_to_le16(freq);
|
||||
} else {
|
||||
txbuf->cmd_tx.peerid =
|
||||
__cpu_to_le32(HTT_INVALID_PEERID);
|
||||
}
|
||||
|
||||
trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid);
|
||||
ath10k_dbg(ar, ATH10K_DBG_HTT,
|
||||
"htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %pad, msdu_paddr %pad vdev %hhu tid %hhu freq %hu\n",
|
||||
flags0, flags1, msdu->len, msdu_id, &frags_paddr,
|
||||
&skb_cb->paddr, vdev_id, tid, freq);
|
||||
ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ",
|
||||
msdu->data, msdu->len);
|
||||
trace_ath10k_tx_hdr(ar, msdu->data, msdu->len);
|
||||
|
|
@ -1303,6 +1549,9 @@ static const struct ath10k_htt_tx_ops htt_tx_ops_32 = {
|
|||
.htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_32,
|
||||
.htt_alloc_frag_desc = ath10k_htt_tx_alloc_cont_frag_desc_32,
|
||||
.htt_free_frag_desc = ath10k_htt_tx_free_cont_frag_desc_32,
|
||||
.htt_tx = ath10k_htt_tx_32,
|
||||
.htt_alloc_txbuff = ath10k_htt_tx_alloc_cont_txbuf_32,
|
||||
.htt_free_txbuff = ath10k_htt_tx_free_cont_txbuf_32,
|
||||
};
|
||||
|
||||
static const struct ath10k_htt_tx_ops htt_tx_ops_64 = {
|
||||
|
|
@ -1310,6 +1559,9 @@ static const struct ath10k_htt_tx_ops htt_tx_ops_64 = {
|
|||
.htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_64,
|
||||
.htt_alloc_frag_desc = ath10k_htt_tx_alloc_cont_frag_desc_64,
|
||||
.htt_free_frag_desc = ath10k_htt_tx_free_cont_frag_desc_64,
|
||||
.htt_tx = ath10k_htt_tx_64,
|
||||
.htt_alloc_txbuff = ath10k_htt_tx_alloc_cont_txbuf_64,
|
||||
.htt_free_txbuff = ath10k_htt_tx_free_cont_txbuf_64,
|
||||
};
|
||||
|
||||
void ath10k_htt_set_tx_ops(struct ath10k_htt *htt)
|
||||
|
|
|
|||
|
|
@ -3597,7 +3597,7 @@ static int ath10k_mac_tx_submit(struct ath10k *ar,
|
|||
|
||||
switch (txpath) {
|
||||
case ATH10K_MAC_TX_HTT:
|
||||
ret = ath10k_htt_tx(htt, txmode, skb);
|
||||
ret = htt->tx_ops->htt_tx(htt, txmode, skb);
|
||||
break;
|
||||
case ATH10K_MAC_TX_HTT_MGMT:
|
||||
ret = ath10k_htt_mgmt_tx(htt, skb);
|
||||
|
|
|
|||
Loading…
Reference in New Issue