x86/fpu: Finish excising 'eagerfpu'
Now that eagerfpu= is gone, remove it from the docs and some comments. Also sync the changes to tools/. Signed-off-by: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Oleg Nesterov <oleg@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Quentin Casasnovas <quentin.casasnovas@oracle.com> Cc: Rik van Riel <riel@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/cf430dd4481d41280e93ac6cf0def1007a67fc8e.1476740397.git.luto@kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -1074,12 +1074,6 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
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nopku [X86] Disable Memory Protection Keys CPU feature found
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in some Intel CPUs.
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eagerfpu= [X86]
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on enable eager fpu restore
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off disable eager fpu restore
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auto selects the default scheme, which automatically
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enables eagerfpu restore for xsaveopt.
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module.async_probe [KNL]
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Enable asynchronous probe on this module.
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@ -104,7 +104,6 @@
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#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */
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#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */
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#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */
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/* free, was #define X86_FEATURE_EAGER_FPU ( 3*32+29) * "eagerfpu" Non lazy FPU restore */
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#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */
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/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
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@ -329,29 +329,6 @@ struct fpu {
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* the registers in the FPU are more recent than this state
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* copy. If the task context-switches away then they get
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* saved here and represent the FPU state.
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*
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* After context switches there may be a (short) time period
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* during which the in-FPU hardware registers are unchanged
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* and still perfectly match this state, if the tasks
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* scheduled afterwards are not using the FPU.
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*
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* This is the 'lazy restore' window of optimization, which
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* we track though 'fpu_fpregs_owner_ctx' and 'fpu->last_cpu'.
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*
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* We detect whether a subsequent task uses the FPU via setting
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* CR0::TS to 1, which causes any FPU use to raise a #NM fault.
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*
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* During this window, if the task gets scheduled again, we
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* might be able to skip having to do a restore from this
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* memory buffer to the hardware registers - at the cost of
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* incurring the overhead of #NM fault traps.
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*
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* Note that on modern CPUs that support the XSAVEOPT (or other
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* optimized XSAVE instructions), we don't use #NM traps anymore,
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* as the hardware can track whether FPU registers need saving
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* or not. On such CPUs we activate the non-lazy ('eagerfpu')
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* logic, which unconditionally saves/restores all FPU state
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* across context switches. (if FPU state exists.)
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*/
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union fpregs_state state;
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/*
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@ -141,8 +141,7 @@ u32 init_pkru_value = PKRU_AD_KEY( 1) | PKRU_AD_KEY( 2) | PKRU_AD_KEY( 3) |
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* Called from the FPU code when creating a fresh set of FPU
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* registers. This is called from a very specific context where
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* we know the FPU regstiers are safe for use and we can use PKRU
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* directly. The fact that PKRU is only available when we are
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* using eagerfpu mode makes this possible.
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* directly.
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*/
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void copy_init_pkru_to_fpregs(void)
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{
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@ -104,7 +104,6 @@
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#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */
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#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */
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#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */
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#define X86_FEATURE_EAGER_FPU ( 3*32+29) /* "eagerfpu" Non lazy FPU restore */
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#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */
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/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
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