ARM: imx6q: clk: Add support for mipi_ipg clock as a shared clock gate
The CG8 field of the CCM CCGR3 register is the 'mipi_core_cfg' gate clock, according to the i.MX6q/sdl reference manuals. This clock is actually the gate for several clocks, including the ipg clock's output. The MIPI DSI host controller embedded in the i.MX6q/sdl SoCs takes the ipg clock as the pclk - the APB clock signal . In order to gate/ungate the ipg clock, this patch adds a new shared clock gate named as "mipi_ipg". Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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@ -419,6 +419,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
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clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2_shared("hsi_tx", "hsi_tx_podf", base + 0x74, 16, &share_count_mipi_core_cfg);
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clk[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_gate2_shared("mipi_core_cfg", "video_27m", base + 0x74, 16, &share_count_mipi_core_cfg);
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clk[IMX6QDL_CLK_MIPI_IPG] = imx_clk_gate2_shared("mipi_ipg", "ipg", base + 0x74, 16, &share_count_mipi_core_cfg);
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if (cpu_is_imx6dl())
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/*
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* The multiplexer and divider of the imx6q clock gpu2d get
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@ -250,6 +250,7 @@
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#define IMX6QDL_CLK_GPT_3M 237
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#define IMX6QDL_CLK_VIDEO_27M 238
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#define IMX6QDL_CLK_MIPI_CORE_CFG 239
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#define IMX6QDL_CLK_END 240
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#define IMX6QDL_CLK_MIPI_IPG 240
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#define IMX6QDL_CLK_END 241
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#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
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