iommu/mediatek: Add mt2712 IOMMU support
The M4U IP blocks in mt2712 is MTK's generation2 M4U which use the ARM Short-descriptor like mt8173, and most of the HW registers are the same. The difference is that there are 2 M4U HWs in mt2712 while there's only one in mt8173. The purpose of 2 M4U HWs is for balance the bandwidth. Normally if there are 2 M4U HWs, there should be 2 iommu domains, each M4U has a iommu domain. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Yong Wu
Joerg Roedel
parent
a9467d9542
commit
e6dec92308
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@ -53,7 +53,11 @@
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#define REG_MMU_CTRL_REG 0x110
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#define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4)
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#define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5)
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#define F_MMU_TF_PROTECT_SEL_SHIFT(data) \
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((data)->m4u_plat == M4U_MT2712 ? 4 : 5)
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/* It's named by F_MMU_TF_PROT_SEL in mt2712. */
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#define F_MMU_TF_PROTECT_SEL(prot, data) \
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(((prot) & 0x3) << F_MMU_TF_PROTECT_SEL_SHIFT(data))
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#define REG_MMU_IVRP_PADDR 0x114
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#define F_MMU_IVRP_PA_SET(pa, ext) (((pa) >> 1) | ((!!(ext)) << 31))
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@ -96,7 +100,7 @@
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* Get the local arbiter ID and the portid within the larb arbiter
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* from mtk_m4u_id which is defined by MTK_M4U_ID.
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*/
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#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0x7)
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#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0xf)
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#define MTK_M4U_TO_PORT(id) ((id) & 0x1f)
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struct mtk_iommu_domain {
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@ -307,10 +311,6 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain,
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data->m4u_dom = NULL;
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return ret;
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}
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} else if (data->m4u_dom != dom) {
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/* All the client devices should be in the same m4u domain */
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dev_err(dev, "try to attach into the error iommu domain\n");
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return -EPERM;
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}
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mtk_iommu_config(data, dev, true);
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@ -470,8 +470,9 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
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return ret;
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}
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regval = F_MMU_PREFETCH_RT_REPLACE_MOD |
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F_MMU_TF_PROTECT_SEL(2);
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regval = F_MMU_TF_PROTECT_SEL(2, data);
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if (data->m4u_plat == M4U_MT8173)
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regval |= F_MMU_PREFETCH_RT_REPLACE_MOD;
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writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
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regval = F_L2_MULIT_HIT_EN |
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@ -493,9 +494,11 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
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writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base, data->enable_4GB),
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data->base + REG_MMU_IVRP_PADDR);
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writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
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writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE);
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/* It's MISC control register whose default value is ok except mt8173.*/
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if (data->m4u_plat == M4U_MT8173)
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writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE);
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if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
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dev_name(data->dev), (void *)data)) {
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@ -527,6 +530,7 @@ static int mtk_iommu_probe(struct platform_device *pdev)
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if (!data)
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return -ENOMEM;
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data->dev = dev;
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data->m4u_plat = (enum mtk_iommu_plat)of_device_get_match_data(dev);
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/* Protect memory. HW will access here while translation fault.*/
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protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL);
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@ -560,6 +564,7 @@ static int mtk_iommu_probe(struct platform_device *pdev)
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for (i = 0; i < larb_nr; i++) {
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struct device_node *larbnode;
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struct platform_device *plarbdev;
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u32 id;
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larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
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if (!larbnode)
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@ -568,17 +573,14 @@ static int mtk_iommu_probe(struct platform_device *pdev)
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if (!of_device_is_available(larbnode))
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continue;
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ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id);
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if (ret)/* The id is consecutive if there is no this property */
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id = i;
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plarbdev = of_find_device_by_node(larbnode);
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if (!plarbdev) {
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plarbdev = of_platform_device_create(
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larbnode, NULL,
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platform_bus_type.dev_root);
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if (!plarbdev) {
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of_node_put(larbnode);
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return -EPROBE_DEFER;
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}
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}
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data->smi_imu.larb_imu[i].dev = &plarbdev->dev;
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if (!plarbdev)
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return -EPROBE_DEFER;
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data->smi_imu.larb_imu[id].dev = &plarbdev->dev;
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component_match_add_release(dev, &match, release_of,
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compare_of, larbnode);
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@ -646,8 +648,6 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
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struct mtk_iommu_suspend_reg *reg = &data->reg;
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void __iomem *base = data->base;
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writel_relaxed(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0],
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base + REG_MMU_PT_BASE_ADDR);
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writel_relaxed(reg->standard_axi_mode,
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base + REG_MMU_STANDARD_AXI_MODE);
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writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
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@ -656,15 +656,19 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
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writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
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writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base, data->enable_4GB),
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base + REG_MMU_IVRP_PADDR);
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if (data->m4u_dom)
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writel(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0],
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base + REG_MMU_PT_BASE_ADDR);
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return 0;
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}
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const struct dev_pm_ops mtk_iommu_pm_ops = {
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static const struct dev_pm_ops mtk_iommu_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)
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};
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static const struct of_device_id mtk_iommu_of_ids[] = {
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{ .compatible = "mediatek,mt8173-m4u", },
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{ .compatible = "mediatek,mt2712-m4u", .data = (void *)M4U_MT2712},
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{ .compatible = "mediatek,mt8173-m4u", .data = (void *)M4U_MT8173},
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{}
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};
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@ -673,27 +677,20 @@ static struct platform_driver mtk_iommu_driver = {
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.remove = mtk_iommu_remove,
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.driver = {
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.name = "mtk-iommu",
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.of_match_table = mtk_iommu_of_ids,
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.of_match_table = of_match_ptr(mtk_iommu_of_ids),
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.pm = &mtk_iommu_pm_ops,
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}
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};
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static int mtk_iommu_init_fn(struct device_node *np)
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static int __init mtk_iommu_init(void)
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{
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int ret;
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struct platform_device *pdev;
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pdev = of_platform_device_create(np, NULL, platform_bus_type.dev_root);
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if (!pdev)
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return -ENOMEM;
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ret = platform_driver_register(&mtk_iommu_driver);
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if (ret) {
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pr_err("%s: Failed to register driver\n", __func__);
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return ret;
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}
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if (ret != 0)
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pr_err("Failed to register MTK IOMMU driver\n");
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return 0;
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return ret;
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}
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IOMMU_OF_DECLARE(mtkm4u, "mediatek,mt8173-m4u", mtk_iommu_init_fn);
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subsys_initcall(mtk_iommu_init)
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@ -34,6 +34,12 @@ struct mtk_iommu_suspend_reg {
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u32 int_main_control;
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};
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enum mtk_iommu_plat {
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M4U_MT2701,
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M4U_MT2712,
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M4U_MT8173,
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};
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struct mtk_iommu_domain;
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struct mtk_iommu_data {
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@ -50,6 +56,7 @@ struct mtk_iommu_data {
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bool tlb_flush_active;
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struct iommu_device iommu;
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enum mtk_iommu_plat m4u_plat;
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};
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static inline int compare_of(struct device *dev, void *data)
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@ -23,7 +23,10 @@
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#include <soc/mediatek/smi.h>
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#include <dt-bindings/memory/mt2701-larb-port.h>
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/* mt8173 */
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#define SMI_LARB_MMU_EN 0xf00
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/* mt2701 */
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#define REG_SMI_SECUR_CON_BASE 0x5c0
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/* every register control 8 port, register offset 0x4 */
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@ -41,6 +44,10 @@
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/* mt2701 domain should be set to 3 */
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#define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1))
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/* mt2712 */
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#define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
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#define F_MMU_EN BIT(0)
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struct mtk_smi_larb_gen {
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bool need_larbid;
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int port_in_larb[MTK_LARB_NR_MAX + 1];
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@ -149,6 +156,15 @@ mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
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struct mtk_smi_iommu *smi_iommu = data;
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unsigned int i;
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if (larb->larb_gen->need_larbid) {
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larb->mmu = &smi_iommu->larb_imu[larb->larbid].mmu;
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return 0;
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}
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/*
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* If there is no larbid property, Loop to find the corresponding
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* iommu information.
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*/
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for (i = 0; i < smi_iommu->larb_nr; i++) {
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if (dev == smi_iommu->larb_imu[i].dev) {
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/* The 'mmu' may be updated in iommu-attach/detach. */
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@ -159,14 +175,33 @@ mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
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return -ENODEV;
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}
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static void mtk_smi_larb_config_port(struct device *dev)
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static void mtk_smi_larb_config_port_mt2712(struct device *dev)
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{
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struct mtk_smi_larb *larb = dev_get_drvdata(dev);
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u32 reg;
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int i;
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/*
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* larb 8/9 is the bdpsys larb, the iommu_en is enabled defaultly.
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* Don't need to set it again.
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*/
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if (larb->larbid == 8 || larb->larbid == 9)
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return;
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for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
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reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
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reg |= F_MMU_EN;
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writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
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}
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}
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static void mtk_smi_larb_config_port_mt8173(struct device *dev)
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{
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struct mtk_smi_larb *larb = dev_get_drvdata(dev);
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writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN);
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}
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static void mtk_smi_larb_config_port_gen1(struct device *dev)
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{
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struct mtk_smi_larb *larb = dev_get_drvdata(dev);
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@ -211,7 +246,7 @@ static const struct component_ops mtk_smi_larb_component_ops = {
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static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = {
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/* mt8173 do not need the port in larb */
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.config_port = mtk_smi_larb_config_port,
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.config_port = mtk_smi_larb_config_port_mt8173,
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};
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static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
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@ -223,6 +258,11 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
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.config_port = mtk_smi_larb_config_port_gen1,
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};
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static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
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.need_larbid = true,
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.config_port = mtk_smi_larb_config_port_mt2712,
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};
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static const struct of_device_id mtk_smi_larb_of_ids[] = {
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{
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.compatible = "mediatek,mt8173-smi-larb",
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@ -232,6 +272,10 @@ static const struct of_device_id mtk_smi_larb_of_ids[] = {
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.compatible = "mediatek,mt2701-smi-larb",
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.data = &mtk_smi_larb_mt2701
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},
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{
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.compatible = "mediatek,mt2712-smi-larb",
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.data = &mtk_smi_larb_mt2712
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},
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{}
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};
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@ -318,6 +362,10 @@ static const struct of_device_id mtk_smi_common_of_ids[] = {
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.compatible = "mediatek,mt2701-smi-common",
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.data = (void *)MTK_SMI_GEN1
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},
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{
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.compatible = "mediatek,mt2712-smi-common",
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.data = (void *)MTK_SMI_GEN2
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},
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{}
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};
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@ -19,7 +19,7 @@
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#ifdef CONFIG_MTK_SMI
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#define MTK_LARB_NR_MAX 8
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#define MTK_LARB_NR_MAX 16
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#define MTK_SMI_MMU_EN(port) BIT(port)
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