i2c: iproc: Add Broadcom iProc I2C Driver
Add initial support to the Broadcom iProc I2C controller found in the iProc family of SoCs. The iProc I2C controller has separate internal TX and RX FIFOs, each has a size of 64 bytes. The iProc I2C controller supports two bus speeds including standard mode (100kHz) and fast mode (400kHz) Signed-off-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Reviewed-by: Kevin Cernekee <cernekee@chromium.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Ray Jui
Wolfram Sang
parent
a93ac5786d
commit
e6e5dd3566
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@ -0,0 +1,37 @@
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Broadcom iProc I2C controller
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Required properties:
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- compatible:
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Must be "brcm,iproc-i2c"
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- reg:
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Define the base and range of the I/O address space that contain the iProc
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I2C controller registers
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- interrupts:
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Should contain the I2C interrupt
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- clock-frequency:
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This is the I2C bus clock. Need to be either 100000 or 400000
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- #address-cells:
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Always 1 (for I2C addresses)
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- #size-cells:
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Always 0
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Example:
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i2c0: i2c@18008000 {
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compatible = "brcm,iproc-i2c";
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reg = <0x18008000 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
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clock-frequency = <100000>;
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codec: wm8750@1a {
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compatible = "wlf,wm8750";
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reg = <0x1a>;
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};
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};
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@ -372,6 +372,16 @@ config I2C_BCM2835
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This support is also available as a module. If so, the module
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will be called i2c-bcm2835.
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config I2C_BCM_IPROC
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tristate "Broadcom iProc I2C controller"
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depends on ARCH_BCM_IPROC || COMPILE_TEST
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default ARCH_BCM_IPROC
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help
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If you say yes to this option, support will be included for the
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Broadcom iProc I2C controller.
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If you don't know what to do here, say N.
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config I2C_BCM_KONA
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tristate "BCM Kona I2C adapter"
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depends on ARCH_BCM_MOBILE
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@ -33,6 +33,7 @@ obj-$(CONFIG_I2C_AT91) += i2c-at91.o
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obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o
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obj-$(CONFIG_I2C_AXXIA) += i2c-axxia.o
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obj-$(CONFIG_I2C_BCM2835) += i2c-bcm2835.o
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obj-$(CONFIG_I2C_BCM_IPROC) += i2c-bcm-iproc.o
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obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o
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obj-$(CONFIG_I2C_CADENCE) += i2c-cadence.o
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obj-$(CONFIG_I2C_CBUS_GPIO) += i2c-cbus-gpio.o
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@ -0,0 +1,461 @@
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/*
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* Copyright (C) 2014 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#define CFG_OFFSET 0x00
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#define CFG_RESET_SHIFT 31
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#define CFG_EN_SHIFT 30
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#define CFG_M_RETRY_CNT_SHIFT 16
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#define CFG_M_RETRY_CNT_MASK 0x0f
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#define TIM_CFG_OFFSET 0x04
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#define TIM_CFG_MODE_400_SHIFT 31
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#define M_FIFO_CTRL_OFFSET 0x0c
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#define M_FIFO_RX_FLUSH_SHIFT 31
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#define M_FIFO_TX_FLUSH_SHIFT 30
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#define M_FIFO_RX_CNT_SHIFT 16
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#define M_FIFO_RX_CNT_MASK 0x7f
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#define M_FIFO_RX_THLD_SHIFT 8
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#define M_FIFO_RX_THLD_MASK 0x3f
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#define M_CMD_OFFSET 0x30
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#define M_CMD_START_BUSY_SHIFT 31
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#define M_CMD_STATUS_SHIFT 25
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#define M_CMD_STATUS_MASK 0x07
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#define M_CMD_STATUS_SUCCESS 0x0
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#define M_CMD_STATUS_LOST_ARB 0x1
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#define M_CMD_STATUS_NACK_ADDR 0x2
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#define M_CMD_STATUS_NACK_DATA 0x3
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#define M_CMD_STATUS_TIMEOUT 0x4
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#define M_CMD_PROTOCOL_SHIFT 9
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#define M_CMD_PROTOCOL_MASK 0xf
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#define M_CMD_PROTOCOL_BLK_WR 0x7
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#define M_CMD_PROTOCOL_BLK_RD 0x8
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#define M_CMD_PEC_SHIFT 8
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#define M_CMD_RD_CNT_SHIFT 0
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#define M_CMD_RD_CNT_MASK 0xff
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#define IE_OFFSET 0x38
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#define IE_M_RX_FIFO_FULL_SHIFT 31
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#define IE_M_RX_THLD_SHIFT 30
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#define IE_M_START_BUSY_SHIFT 28
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#define IS_OFFSET 0x3c
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#define IS_M_RX_FIFO_FULL_SHIFT 31
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#define IS_M_RX_THLD_SHIFT 30
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#define IS_M_START_BUSY_SHIFT 28
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#define M_TX_OFFSET 0x40
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#define M_TX_WR_STATUS_SHIFT 31
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#define M_TX_DATA_SHIFT 0
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#define M_TX_DATA_MASK 0xff
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#define M_RX_OFFSET 0x44
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#define M_RX_STATUS_SHIFT 30
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#define M_RX_STATUS_MASK 0x03
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#define M_RX_PEC_ERR_SHIFT 29
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#define M_RX_DATA_SHIFT 0
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#define M_RX_DATA_MASK 0xff
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#define I2C_TIMEOUT_MESC 100
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#define M_TX_RX_FIFO_SIZE 64
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enum bus_speed_index {
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I2C_SPD_100K = 0,
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I2C_SPD_400K,
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};
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struct bcm_iproc_i2c_dev {
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struct device *device;
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int irq;
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void __iomem *base;
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struct i2c_adapter adapter;
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struct completion done;
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int xfer_is_done;
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};
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/*
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* Can be expanded in the future if more interrupt status bits are utilized
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*/
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#define ISR_MASK (1 << IS_M_START_BUSY_SHIFT)
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static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
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{
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struct bcm_iproc_i2c_dev *iproc_i2c = data;
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u32 status = readl(iproc_i2c->base + IS_OFFSET);
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status &= ISR_MASK;
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if (!status)
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return IRQ_NONE;
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writel(status, iproc_i2c->base + IS_OFFSET);
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iproc_i2c->xfer_is_done = 1;
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complete_all(&iproc_i2c->done);
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return IRQ_HANDLED;
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}
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static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
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struct i2c_msg *msg)
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{
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u32 val;
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val = readl(iproc_i2c->base + M_CMD_OFFSET);
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val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK;
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switch (val) {
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case M_CMD_STATUS_SUCCESS:
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return 0;
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case M_CMD_STATUS_LOST_ARB:
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dev_dbg(iproc_i2c->device, "lost bus arbitration\n");
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return -EAGAIN;
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case M_CMD_STATUS_NACK_ADDR:
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dev_dbg(iproc_i2c->device, "NAK addr:0x%02x\n", msg->addr);
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return -ENXIO;
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case M_CMD_STATUS_NACK_DATA:
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dev_dbg(iproc_i2c->device, "NAK data\n");
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return -ENXIO;
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case M_CMD_STATUS_TIMEOUT:
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dev_dbg(iproc_i2c->device, "bus timeout\n");
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return -ETIMEDOUT;
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default:
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dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val);
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return -EIO;
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}
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}
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static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c,
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struct i2c_msg *msg)
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{
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int ret, i;
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u8 addr;
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u32 val;
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unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MESC);
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/* need to reserve one byte in the FIFO for the slave address */
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if (msg->len > M_TX_RX_FIFO_SIZE - 1) {
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dev_err(iproc_i2c->device,
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"only support data length up to %u bytes\n",
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M_TX_RX_FIFO_SIZE - 1);
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return -EOPNOTSUPP;
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}
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/* check if bus is busy */
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if (!!(readl(iproc_i2c->base + M_CMD_OFFSET) &
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BIT(M_CMD_START_BUSY_SHIFT))) {
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dev_warn(iproc_i2c->device, "bus is busy\n");
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return -EBUSY;
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}
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/* format and load slave address into the TX FIFO */
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addr = msg->addr << 1 | (msg->flags & I2C_M_RD ? 1 : 0);
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writel(addr, iproc_i2c->base + M_TX_OFFSET);
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/* for a write transaction, load data into the TX FIFO */
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if (!(msg->flags & I2C_M_RD)) {
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for (i = 0; i < msg->len; i++) {
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val = msg->buf[i];
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/* mark the last byte */
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if (i == msg->len - 1)
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val |= 1 << M_TX_WR_STATUS_SHIFT;
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writel(val, iproc_i2c->base + M_TX_OFFSET);
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}
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}
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/* mark as incomplete before starting the transaction */
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reinit_completion(&iproc_i2c->done);
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iproc_i2c->xfer_is_done = 0;
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/*
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* Enable the "start busy" interrupt, which will be triggered after the
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* transaction is done, i.e., the internal start_busy bit, transitions
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* from 1 to 0.
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*/
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writel(1 << IE_M_START_BUSY_SHIFT, iproc_i2c->base + IE_OFFSET);
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/*
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* Now we can activate the transfer. For a read operation, specify the
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* number of bytes to read
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*/
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val = 1 << M_CMD_START_BUSY_SHIFT;
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if (msg->flags & I2C_M_RD) {
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val |= (M_CMD_PROTOCOL_BLK_RD << M_CMD_PROTOCOL_SHIFT) |
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(msg->len << M_CMD_RD_CNT_SHIFT);
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} else {
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val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT);
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}
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writel(val, iproc_i2c->base + M_CMD_OFFSET);
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time_left = wait_for_completion_timeout(&iproc_i2c->done, time_left);
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/* disable all interrupts */
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writel(0, iproc_i2c->base + IE_OFFSET);
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/* read it back to flush the write */
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readl(iproc_i2c->base + IE_OFFSET);
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/* make sure the interrupt handler isn't running */
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synchronize_irq(iproc_i2c->irq);
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if (!time_left && !iproc_i2c->xfer_is_done) {
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dev_err(iproc_i2c->device, "transaction timed out\n");
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/* flush FIFOs */
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val = (1 << M_FIFO_RX_FLUSH_SHIFT) |
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(1 << M_FIFO_TX_FLUSH_SHIFT);
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writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
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return -ETIMEDOUT;
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}
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ret = bcm_iproc_i2c_check_status(iproc_i2c, msg);
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if (ret) {
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/* flush both TX/RX FIFOs */
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val = (1 << M_FIFO_RX_FLUSH_SHIFT) |
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(1 << M_FIFO_TX_FLUSH_SHIFT);
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writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
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return ret;
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}
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/*
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* For a read operation, we now need to load the data from FIFO
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* into the memory buffer
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*/
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if (msg->flags & I2C_M_RD) {
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for (i = 0; i < msg->len; i++) {
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msg->buf[i] = (readl(iproc_i2c->base + M_RX_OFFSET) >>
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M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
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}
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}
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return 0;
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}
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static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter,
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struct i2c_msg msgs[], int num)
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{
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struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adapter);
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int ret, i;
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/* go through all messages */
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for (i = 0; i < num; i++) {
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ret = bcm_iproc_i2c_xfer_single_msg(iproc_i2c, &msgs[i]);
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if (ret) {
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dev_dbg(iproc_i2c->device, "xfer failed\n");
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return ret;
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}
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}
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return num;
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}
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static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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static const struct i2c_algorithm bcm_iproc_algo = {
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.master_xfer = bcm_iproc_i2c_xfer,
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.functionality = bcm_iproc_i2c_functionality,
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};
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static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)
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{
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unsigned int bus_speed;
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u32 val;
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int ret = of_property_read_u32(iproc_i2c->device->of_node,
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"clock-frequency", &bus_speed);
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if (ret < 0) {
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dev_info(iproc_i2c->device,
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"unable to interpret clock-frequency DT property\n");
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bus_speed = 100000;
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}
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if (bus_speed < 100000) {
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dev_err(iproc_i2c->device, "%d Hz bus speed not supported\n",
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bus_speed);
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dev_err(iproc_i2c->device,
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"valid speeds are 100khz and 400khz\n");
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return -EINVAL;
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} else if (bus_speed < 400000) {
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bus_speed = 100000;
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} else {
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bus_speed = 400000;
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}
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val = readl(iproc_i2c->base + TIM_CFG_OFFSET);
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val &= ~(1 << TIM_CFG_MODE_400_SHIFT);
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val |= (bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT;
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writel(val, iproc_i2c->base + TIM_CFG_OFFSET);
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dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed);
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return 0;
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}
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static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c)
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{
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u32 val;
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/* put controller in reset */
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val = readl(iproc_i2c->base + CFG_OFFSET);
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val |= 1 << CFG_RESET_SHIFT;
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val &= ~(1 << CFG_EN_SHIFT);
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writel(val, iproc_i2c->base + CFG_OFFSET);
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/* wait 100 usec per spec */
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udelay(100);
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/* bring controller out of reset */
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val &= ~(1 << CFG_RESET_SHIFT);
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writel(val, iproc_i2c->base + CFG_OFFSET);
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/* flush TX/RX FIFOs and set RX FIFO threshold to zero */
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val = (1 << M_FIFO_RX_FLUSH_SHIFT) | (1 << M_FIFO_TX_FLUSH_SHIFT);
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writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
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/* disable all interrupts */
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writel(0, iproc_i2c->base + IE_OFFSET);
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/* clear all pending interrupts */
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writel(0xffffffff, iproc_i2c->base + IS_OFFSET);
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return 0;
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}
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static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
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bool enable)
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{
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u32 val;
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val = readl(iproc_i2c->base + CFG_OFFSET);
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if (enable)
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val |= BIT(CFG_EN_SHIFT);
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else
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val &= ~BIT(CFG_EN_SHIFT);
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writel(val, iproc_i2c->base + CFG_OFFSET);
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}
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static int bcm_iproc_i2c_probe(struct platform_device *pdev)
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{
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int irq, ret = 0;
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struct bcm_iproc_i2c_dev *iproc_i2c;
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struct i2c_adapter *adap;
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struct resource *res;
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iproc_i2c = devm_kzalloc(&pdev->dev, sizeof(*iproc_i2c),
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GFP_KERNEL);
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||||
if (!iproc_i2c)
|
||||
return -ENOMEM;
|
||||
|
||||
platform_set_drvdata(pdev, iproc_i2c);
|
||||
iproc_i2c->device = &pdev->dev;
|
||||
init_completion(&iproc_i2c->done);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
iproc_i2c->base = devm_ioremap_resource(iproc_i2c->device, res);
|
||||
if (IS_ERR(iproc_i2c->base))
|
||||
return PTR_ERR(iproc_i2c->base);
|
||||
|
||||
ret = bcm_iproc_i2c_init(iproc_i2c);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = bcm_iproc_i2c_cfg_speed(iproc_i2c);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq <= 0) {
|
||||
dev_err(iproc_i2c->device, "no irq resource\n");
|
||||
return irq;
|
||||
}
|
||||
iproc_i2c->irq = irq;
|
||||
|
||||
ret = devm_request_irq(iproc_i2c->device, irq, bcm_iproc_i2c_isr, 0,
|
||||
pdev->name, iproc_i2c);
|
||||
if (ret < 0) {
|
||||
dev_err(iproc_i2c->device, "unable to request irq %i\n", irq);
|
||||
return ret;
|
||||
}
|
||||
|
||||
bcm_iproc_i2c_enable_disable(iproc_i2c, true);
|
||||
|
||||
adap = &iproc_i2c->adapter;
|
||||
i2c_set_adapdata(adap, iproc_i2c);
|
||||
strlcpy(adap->name, "Broadcom iProc I2C adapter", sizeof(adap->name));
|
||||
adap->algo = &bcm_iproc_algo;
|
||||
adap->dev.parent = &pdev->dev;
|
||||
adap->dev.of_node = pdev->dev.of_node;
|
||||
|
||||
ret = i2c_add_adapter(adap);
|
||||
if (ret) {
|
||||
dev_err(iproc_i2c->device, "failed to add adapter\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm_iproc_i2c_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
|
||||
|
||||
/* make sure there's no pending interrupt when we remove the adapter */
|
||||
writel(0, iproc_i2c->base + IE_OFFSET);
|
||||
readl(iproc_i2c->base + IE_OFFSET);
|
||||
synchronize_irq(iproc_i2c->irq);
|
||||
|
||||
i2c_del_adapter(&iproc_i2c->adapter);
|
||||
bcm_iproc_i2c_enable_disable(iproc_i2c, false);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id bcm_iproc_i2c_of_match[] = {
|
||||
{ .compatible = "brcm,iproc-i2c" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match);
|
||||
|
||||
static struct platform_driver bcm_iproc_i2c_driver = {
|
||||
.driver = {
|
||||
.name = "bcm-iproc-i2c",
|
||||
.of_match_table = bcm_iproc_i2c_of_match,
|
||||
},
|
||||
.probe = bcm_iproc_i2c_probe,
|
||||
.remove = bcm_iproc_i2c_remove,
|
||||
};
|
||||
module_platform_driver(bcm_iproc_i2c_driver);
|
||||
|
||||
MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
|
||||
MODULE_DESCRIPTION("Broadcom iProc I2C Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue