pinctrl: mediatek: add mtk_pctrl_spec_pull_set_samereg common code
Several mediatek soc use similar pull setting procedure as mt8173, the pupd enable and resistance setting are in the same register. Add common code mtk_pctrl_spec_pull_set_samereg out of spec_pull_set in mt8173 to handle this case, so future soc driver can use it. Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Yingjoe Chen
Linus Walleij
parent
4b9b526846
commit
e73fe2713f
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@ -47,130 +47,54 @@ struct mtk_pin_ies_smt_set {
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.offset = _offset, \
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}
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/**
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* struct mtk_pin_spec_pupd_set - For special pins' pull up/down setting.
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* @pin: The pin number.
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* @offset: The offset of special pull up/down setting register.
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* @pupd_bit: The pull up/down bit in this register.
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* @r0_bit: The r0 bit of pull resistor.
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* @r1_bit: The r1 bit of pull resistor.
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*/
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struct mtk_pin_spec_pupd_set {
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unsigned int pin;
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unsigned int offset;
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unsigned char pupd_bit;
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unsigned char r1_bit;
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unsigned char r0_bit;
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static const struct mtk_pin_spec_pupd_set_samereg mt8173_spec_pupd[] = {
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MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */
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MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4), /* KROW1 */
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MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */
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MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0), /* KCOL0 */
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MTK_PIN_PUPD_SPEC_SR(123, 0xe10, 6, 5, 4), /* KCOL1 */
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MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */
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MTK_PIN_PUPD_SPEC_SR(67, 0xd10, 2, 1, 0), /* ms0 DS */
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MTK_PIN_PUPD_SPEC_SR(68, 0xd00, 2, 1, 0), /* ms0 RST */
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MTK_PIN_PUPD_SPEC_SR(66, 0xc10, 2, 1, 0), /* ms0 cmd */
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MTK_PIN_PUPD_SPEC_SR(65, 0xc00, 2, 1, 0), /* ms0 clk */
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MTK_PIN_PUPD_SPEC_SR(57, 0xc20, 2, 1, 0), /* ms0 data0 */
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MTK_PIN_PUPD_SPEC_SR(58, 0xc20, 2, 1, 0), /* ms0 data1 */
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MTK_PIN_PUPD_SPEC_SR(59, 0xc20, 2, 1, 0), /* ms0 data2 */
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MTK_PIN_PUPD_SPEC_SR(60, 0xc20, 2, 1, 0), /* ms0 data3 */
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MTK_PIN_PUPD_SPEC_SR(61, 0xc20, 2, 1, 0), /* ms0 data4 */
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MTK_PIN_PUPD_SPEC_SR(62, 0xc20, 2, 1, 0), /* ms0 data5 */
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MTK_PIN_PUPD_SPEC_SR(63, 0xc20, 2, 1, 0), /* ms0 data6 */
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MTK_PIN_PUPD_SPEC_SR(64, 0xc20, 2, 1, 0), /* ms0 data7 */
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MTK_PIN_PUPD_SPEC_SR(78, 0xc50, 2, 1, 0), /* ms1 cmd */
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MTK_PIN_PUPD_SPEC_SR(73, 0xd20, 2, 1, 0), /* ms1 dat0 */
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MTK_PIN_PUPD_SPEC_SR(74, 0xd20, 6, 5, 4), /* ms1 dat1 */
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MTK_PIN_PUPD_SPEC_SR(75, 0xd20, 10, 9, 8), /* ms1 dat2 */
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MTK_PIN_PUPD_SPEC_SR(76, 0xd20, 14, 13, 12), /* ms1 dat3 */
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MTK_PIN_PUPD_SPEC_SR(77, 0xc40, 2, 1, 0), /* ms1 clk */
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MTK_PIN_PUPD_SPEC_SR(100, 0xd40, 2, 1, 0), /* ms2 dat0 */
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MTK_PIN_PUPD_SPEC_SR(101, 0xd40, 6, 5, 4), /* ms2 dat1 */
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MTK_PIN_PUPD_SPEC_SR(102, 0xd40, 10, 9, 8), /* ms2 dat2 */
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MTK_PIN_PUPD_SPEC_SR(103, 0xd40, 14, 13, 12), /* ms2 dat3 */
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MTK_PIN_PUPD_SPEC_SR(104, 0xc80, 2, 1, 0), /* ms2 clk */
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MTK_PIN_PUPD_SPEC_SR(105, 0xc90, 2, 1, 0), /* ms2 cmd */
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MTK_PIN_PUPD_SPEC_SR(22, 0xd60, 2, 1, 0), /* ms3 dat0 */
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MTK_PIN_PUPD_SPEC_SR(23, 0xd60, 6, 5, 4), /* ms3 dat1 */
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MTK_PIN_PUPD_SPEC_SR(24, 0xd60, 10, 9, 8), /* ms3 dat2 */
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MTK_PIN_PUPD_SPEC_SR(25, 0xd60, 14, 13, 12), /* ms3 dat3 */
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MTK_PIN_PUPD_SPEC_SR(26, 0xcc0, 2, 1, 0), /* ms3 clk */
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MTK_PIN_PUPD_SPEC_SR(27, 0xcd0, 2, 1, 0) /* ms3 cmd */
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};
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#define MTK_PIN_PUPD_SPEC(_pin, _offset, _pupd, _r1, _r0) \
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{ \
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.pin = _pin, \
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.offset = _offset, \
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.pupd_bit = _pupd, \
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.r1_bit = _r1, \
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.r0_bit = _r0, \
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}
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static const struct mtk_pin_spec_pupd_set mt8173_spec_pupd[] = {
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MTK_PIN_PUPD_SPEC(119, 0xe00, 2, 1, 0), /* KROW0 */
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MTK_PIN_PUPD_SPEC(120, 0xe00, 6, 5, 4), /* KROW1 */
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MTK_PIN_PUPD_SPEC(121, 0xe00, 10, 9, 8), /* KROW2 */
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MTK_PIN_PUPD_SPEC(122, 0xe10, 2, 1, 0), /* KCOL0 */
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MTK_PIN_PUPD_SPEC(123, 0xe10, 6, 5, 4), /* KCOL1 */
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MTK_PIN_PUPD_SPEC(124, 0xe10, 10, 9, 8), /* KCOL2 */
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MTK_PIN_PUPD_SPEC(67, 0xd10, 2, 1, 0), /* ms0 DS */
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MTK_PIN_PUPD_SPEC(68, 0xd00, 2, 1, 0), /* ms0 RST */
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MTK_PIN_PUPD_SPEC(66, 0xc10, 2, 1, 0), /* ms0 cmd */
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MTK_PIN_PUPD_SPEC(65, 0xc00, 2, 1, 0), /* ms0 clk */
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MTK_PIN_PUPD_SPEC(57, 0xc20, 2, 1, 0), /* ms0 data0 */
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MTK_PIN_PUPD_SPEC(58, 0xc20, 2, 1, 0), /* ms0 data1 */
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MTK_PIN_PUPD_SPEC(59, 0xc20, 2, 1, 0), /* ms0 data2 */
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MTK_PIN_PUPD_SPEC(60, 0xc20, 2, 1, 0), /* ms0 data3 */
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MTK_PIN_PUPD_SPEC(61, 0xc20, 2, 1, 0), /* ms0 data4 */
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MTK_PIN_PUPD_SPEC(62, 0xc20, 2, 1, 0), /* ms0 data5 */
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MTK_PIN_PUPD_SPEC(63, 0xc20, 2, 1, 0), /* ms0 data6 */
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MTK_PIN_PUPD_SPEC(64, 0xc20, 2, 1, 0), /* ms0 data7 */
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MTK_PIN_PUPD_SPEC(78, 0xc50, 2, 1, 0), /* ms1 cmd */
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MTK_PIN_PUPD_SPEC(73, 0xd20, 2, 1, 0), /* ms1 dat0 */
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MTK_PIN_PUPD_SPEC(74, 0xd20, 6, 5, 4), /* ms1 dat1 */
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MTK_PIN_PUPD_SPEC(75, 0xd20, 10, 9, 8), /* ms1 dat2 */
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MTK_PIN_PUPD_SPEC(76, 0xd20, 14, 13, 12), /* ms1 dat3 */
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MTK_PIN_PUPD_SPEC(77, 0xc40, 2, 1, 0), /* ms1 clk */
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MTK_PIN_PUPD_SPEC(100, 0xd40, 2, 1, 0), /* ms2 dat0 */
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MTK_PIN_PUPD_SPEC(101, 0xd40, 6, 5, 4), /* ms2 dat1 */
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MTK_PIN_PUPD_SPEC(102, 0xd40, 10, 9, 8), /* ms2 dat2 */
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MTK_PIN_PUPD_SPEC(103, 0xd40, 14, 13, 12), /* ms2 dat3 */
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MTK_PIN_PUPD_SPEC(104, 0xc80, 2, 1, 0), /* ms2 clk */
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MTK_PIN_PUPD_SPEC(105, 0xc90, 2, 1, 0), /* ms2 cmd */
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MTK_PIN_PUPD_SPEC(22, 0xd60, 2, 1, 0), /* ms3 dat0 */
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MTK_PIN_PUPD_SPEC(23, 0xd60, 6, 5, 4), /* ms3 dat1 */
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MTK_PIN_PUPD_SPEC(24, 0xd60, 10, 9, 8), /* ms3 dat2 */
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MTK_PIN_PUPD_SPEC(25, 0xd60, 14, 13, 12), /* ms3 dat3 */
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MTK_PIN_PUPD_SPEC(26, 0xcc0, 2, 1, 0), /* ms3 clk */
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MTK_PIN_PUPD_SPEC(27, 0xcd0, 2, 1, 0) /* ms3 cmd */
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};
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static int spec_pull_set(struct regmap *regmap, unsigned int pin,
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static int mt8173_spec_pull_set(struct regmap *regmap, unsigned int pin,
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unsigned char align, bool isup, unsigned int r1r0)
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{
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unsigned int i;
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unsigned int reg_pupd, reg_set, reg_rst;
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unsigned int bit_pupd, bit_r0, bit_r1;
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const struct mtk_pin_spec_pupd_set *spec_pupd_pin;
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bool find = false;
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for (i = 0; i < ARRAY_SIZE(mt8173_spec_pupd); i++) {
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if (pin == mt8173_spec_pupd[i].pin) {
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find = true;
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break;
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}
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}
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if (!find)
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return -EINVAL;
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spec_pupd_pin = mt8173_spec_pupd + i;
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reg_set = spec_pupd_pin->offset + align;
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reg_rst = spec_pupd_pin->offset + (align << 1);
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if (isup)
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reg_pupd = reg_rst;
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else
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reg_pupd = reg_set;
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bit_pupd = BIT(spec_pupd_pin->pupd_bit);
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regmap_write(regmap, reg_pupd, bit_pupd);
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bit_r0 = BIT(spec_pupd_pin->r0_bit);
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bit_r1 = BIT(spec_pupd_pin->r1_bit);
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switch (r1r0) {
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case MTK_PUPD_SET_R1R0_00:
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regmap_write(regmap, reg_rst, bit_r0);
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regmap_write(regmap, reg_rst, bit_r1);
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break;
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case MTK_PUPD_SET_R1R0_01:
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regmap_write(regmap, reg_set, bit_r0);
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regmap_write(regmap, reg_rst, bit_r1);
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break;
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case MTK_PUPD_SET_R1R0_10:
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regmap_write(regmap, reg_rst, bit_r0);
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regmap_write(regmap, reg_set, bit_r1);
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break;
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case MTK_PUPD_SET_R1R0_11:
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regmap_write(regmap, reg_set, bit_r0);
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regmap_write(regmap, reg_set, bit_r1);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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return mtk_pctrl_spec_pull_set_samereg(regmap, mt8173_spec_pupd,
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ARRAY_SIZE(mt8173_spec_pupd), pin, align, isup, r1r0);
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}
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static const struct mtk_pin_ies_smt_set mt8173_ies_smt_set[] = {
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@ -382,7 +306,7 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = {
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.n_grp_cls = ARRAY_SIZE(mt8173_drv_grp),
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.pin_drv_grp = mt8173_pin_drv,
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.n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv),
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.spec_pull_set = spec_pull_set,
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.spec_pull_set = mt8173_spec_pull_set,
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.spec_ies_smt_set = spec_ies_smt_set,
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.dir_offset = 0x0000,
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.pullen_offset = 0x0100,
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@ -186,6 +186,66 @@ static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl,
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return -EINVAL;
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}
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int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
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const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
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unsigned int info_num, unsigned int pin,
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unsigned char align, bool isup, unsigned int r1r0)
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{
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unsigned int i;
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unsigned int reg_pupd, reg_set, reg_rst;
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unsigned int bit_pupd, bit_r0, bit_r1;
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const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin;
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bool find = false;
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for (i = 0; i < info_num; i++) {
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if (pin == pupd_infos[i].pin) {
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find = true;
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break;
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}
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}
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if (!find)
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return -EINVAL;
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spec_pupd_pin = pupd_infos + i;
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reg_set = spec_pupd_pin->offset + align;
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reg_rst = spec_pupd_pin->offset + (align << 1);
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if (isup)
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reg_pupd = reg_rst;
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else
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reg_pupd = reg_set;
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bit_pupd = BIT(spec_pupd_pin->pupd_bit);
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regmap_write(regmap, reg_pupd, bit_pupd);
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bit_r0 = BIT(spec_pupd_pin->r0_bit);
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bit_r1 = BIT(spec_pupd_pin->r1_bit);
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switch (r1r0) {
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case MTK_PUPD_SET_R1R0_00:
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regmap_write(regmap, reg_rst, bit_r0);
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regmap_write(regmap, reg_rst, bit_r1);
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break;
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case MTK_PUPD_SET_R1R0_01:
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regmap_write(regmap, reg_set, bit_r0);
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regmap_write(regmap, reg_rst, bit_r1);
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break;
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case MTK_PUPD_SET_R1R0_10:
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regmap_write(regmap, reg_rst, bit_r0);
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regmap_write(regmap, reg_set, bit_r1);
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break;
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case MTK_PUPD_SET_R1R0_11:
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regmap_write(regmap, reg_set, bit_r0);
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regmap_write(regmap, reg_set, bit_r1);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
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unsigned int pin, bool enable, bool isup, unsigned int arg)
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{
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@ -117,6 +117,32 @@ struct mtk_pin_drv_grp {
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.grp = _grp, \
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}
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/**
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* struct mtk_pin_spec_pupd_set_samereg
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* - For special pins' pull up/down setting which resides in same register
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* @pin: The pin number.
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* @offset: The offset of special pull up/down setting register.
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* @pupd_bit: The pull up/down bit in this register.
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* @r0_bit: The r0 bit of pull resistor.
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* @r1_bit: The r1 bit of pull resistor.
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*/
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struct mtk_pin_spec_pupd_set_samereg {
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unsigned short pin;
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unsigned short offset;
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unsigned char pupd_bit;
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unsigned char r1_bit;
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unsigned char r0_bit;
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};
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#define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0) \
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{ \
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.pin = _pin, \
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.offset = _offset, \
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.pupd_bit = _pupd, \
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.r1_bit = _r1, \
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.r0_bit = _r0, \
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}
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struct mtk_eint_offsets {
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const char *name;
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unsigned int stat;
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@ -220,4 +246,9 @@ struct mtk_pinctrl {
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int mtk_pctrl_init(struct platform_device *pdev,
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const struct mtk_pinctrl_devdata *data);
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int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
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const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
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unsigned int info_num, unsigned int pin,
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unsigned char align, bool isup, unsigned int r1r0);
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#endif /* __PINCTRL_MTK_COMMON_H */
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