pci-v4.14-fixes-5
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commit
e837d9134b
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@ -935,6 +935,8 @@ static int advk_pcie_probe(struct platform_device *pdev)
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bridge->sysdata = pcie;
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bridge->busnr = 0;
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bridge->ops = &advk_pcie_ops;
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bridge->map_irq = of_irq_parse_and_map_pci;
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bridge->swizzle_irq = pci_common_swizzle;
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ret = pci_scan_root_bus_bridge(bridge);
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if (ret < 0) {
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@ -233,6 +233,7 @@ struct tegra_msi {
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struct msi_controller chip;
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DECLARE_BITMAP(used, INT_PCI_MSI_NR);
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struct irq_domain *domain;
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unsigned long pages;
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struct mutex lock;
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u64 phys;
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int irq;
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@ -1529,22 +1530,9 @@ static int tegra_pcie_enable_msi(struct tegra_pcie *pcie)
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goto err;
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}
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/*
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* The PCI host bridge on Tegra contains some logic that intercepts
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* MSI writes, which means that the MSI target address doesn't have
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* to point to actual physical memory. Rather than allocating one 4
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* KiB page of system memory that's never used, we can simply pick
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* an arbitrary address within an area reserved for system memory
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* in the FPCI address map.
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*
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* However, in order to avoid confusion, we pick an address that
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* doesn't map to physical memory. The FPCI address map reserves a
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* 1012 GiB region for system memory and memory-mapped I/O. Since
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* none of the Tegra SoCs that contain this PCI host bridge can
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* address more than 16 GiB of system memory, the last 4 KiB of
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* these 1012 GiB is a good candidate.
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*/
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msi->phys = 0xfcfffff000;
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/* setup AFI/FPCI range */
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msi->pages = __get_free_pages(GFP_KERNEL, 0);
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msi->phys = virt_to_phys((void *)msi->pages);
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afi_writel(pcie, msi->phys >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST);
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afi_writel(pcie, msi->phys, AFI_MSI_AXI_BAR_ST);
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@ -1596,6 +1584,8 @@ static int tegra_pcie_disable_msi(struct tegra_pcie *pcie)
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afi_writel(pcie, 0, AFI_MSI_EN_VEC6);
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afi_writel(pcie, 0, AFI_MSI_EN_VEC7);
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free_pages(msi->pages, 0);
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if (msi->irq > 0)
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free_irq(msi->irq, pcie);
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