drm/meson: fix vsync buffer update
The plane buffer address/stride/height was incorrectly updated in the
plane_atomic_update operation instead of the vsync irq.
This patch delays this operation in the vsync irq along with the
other plane delayed setup.
This issue was masked using legacy framebuffer and X11 modesetting, but
is clearly visible using gbm rendering when buffer is submitted late after
vblank, like using software decoding and OpenGL rendering in Kodi.
With this patch, tearing and other artifacts disappears completely.
Cc: Michal Lazo <michal.lazo@gmail.com>
Fixes: bbbe775ec5
("drm: Add support for Amlogic Meson Graphic Controller")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/1518689976-23292-1-git-send-email-narmstrong@baylibre.com
This commit is contained in:
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@ -36,6 +36,7 @@
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#include "meson_venc.h"
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#include "meson_vpp.h"
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#include "meson_viu.h"
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#include "meson_canvas.h"
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#include "meson_registers.h"
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/* CRTC definition */
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@ -192,6 +193,11 @@ void meson_crtc_irq(struct meson_drm *priv)
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} else
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meson_vpp_disable_interlace_vscaler_osd1(priv);
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meson_canvas_setup(priv, MESON_CANVAS_ID_OSD1,
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priv->viu.osd1_addr, priv->viu.osd1_stride,
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priv->viu.osd1_height, MESON_CANVAS_WRAP_NONE,
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MESON_CANVAS_BLKMODE_LINEAR);
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/* Enable OSD1 */
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writel_bits_relaxed(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND,
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priv->io_base + _REG(VPP_MISC));
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@ -43,6 +43,9 @@ struct meson_drm {
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bool osd1_commit;
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uint32_t osd1_ctrl_stat;
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uint32_t osd1_blk0_cfg[5];
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uint32_t osd1_addr;
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uint32_t osd1_stride;
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uint32_t osd1_height;
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} viu;
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struct {
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@ -164,10 +164,9 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
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/* Update Canvas with buffer address */
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gem = drm_fb_cma_get_gem_obj(fb, 0);
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meson_canvas_setup(priv, MESON_CANVAS_ID_OSD1,
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gem->paddr, fb->pitches[0],
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fb->height, MESON_CANVAS_WRAP_NONE,
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MESON_CANVAS_BLKMODE_LINEAR);
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priv->viu.osd1_addr = gem->paddr;
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priv->viu.osd1_stride = fb->pitches[0];
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priv->viu.osd1_height = fb->height;
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spin_unlock_irqrestore(&priv->drm->event_lock, flags);
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}
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