powerpc/dts: Remove T4240 emulator support
Probably we should have not upstreamed this in the first place Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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Emil Medve
Scott Wood
parent
6d5f6a0eba
commit
e8d2081bb4
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@ -1,281 +0,0 @@
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/*
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* T4240 emulator Device Tree Source
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*
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* Copyright 2013 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/dts-v1/;
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/include/ "fsl/e6500_power_isa.dtsi"
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/ {
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compatible = "fsl,T4240";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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aliases {
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ccsr = &soc;
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serial0 = &serial0;
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serial1 = &serial1;
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serial2 = &serial2;
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serial3 = &serial3;
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dma0 = &dma0;
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dma1 = &dma1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: PowerPC,e6500@0 {
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device_type = "cpu";
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reg = <0 1>;
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next-level-cache = <&L2_1>;
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fsl,portid-mapping = <0x80000000>;
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};
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cpu1: PowerPC,e6500@2 {
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device_type = "cpu";
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reg = <2 3>;
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next-level-cache = <&L2_1>;
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fsl,portid-mapping = <0x80000000>;
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};
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cpu2: PowerPC,e6500@4 {
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device_type = "cpu";
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reg = <4 5>;
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next-level-cache = <&L2_1>;
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fsl,portid-mapping = <0x80000000>;
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};
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cpu3: PowerPC,e6500@6 {
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device_type = "cpu";
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reg = <6 7>;
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next-level-cache = <&L2_1>;
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fsl,portid-mapping = <0x80000000>;
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};
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cpu4: PowerPC,e6500@8 {
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device_type = "cpu";
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reg = <8 9>;
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next-level-cache = <&L2_2>;
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fsl,portid-mapping = <0x40000000>;
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};
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cpu5: PowerPC,e6500@10 {
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device_type = "cpu";
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reg = <10 11>;
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next-level-cache = <&L2_2>;
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fsl,portid-mapping = <0x40000000>;
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};
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cpu6: PowerPC,e6500@12 {
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device_type = "cpu";
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reg = <12 13>;
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next-level-cache = <&L2_2>;
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fsl,portid-mapping = <0x40000000>;
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};
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cpu7: PowerPC,e6500@14 {
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device_type = "cpu";
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reg = <14 15>;
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next-level-cache = <&L2_2>;
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fsl,portid-mapping = <0x40000000>;
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};
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cpu8: PowerPC,e6500@16 {
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device_type = "cpu";
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reg = <16 17>;
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next-level-cache = <&L2_3>;
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fsl,portid-mapping = <0x20000000>;
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};
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cpu9: PowerPC,e6500@18 {
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device_type = "cpu";
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reg = <18 19>;
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next-level-cache = <&L2_3>;
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fsl,portid-mapping = <0x20000000>;
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};
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cpu10: PowerPC,e6500@20 {
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device_type = "cpu";
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reg = <20 21>;
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next-level-cache = <&L2_3>;
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fsl,portid-mapping = <0x20000000>;
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};
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cpu11: PowerPC,e6500@22 {
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device_type = "cpu";
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reg = <22 23>;
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next-level-cache = <&L2_3>;
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fsl,portid-mapping = <0x20000000>;
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};
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};
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};
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/ {
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model = "fsl,T4240QDS";
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compatible = "fsl,T4240EMU", "fsl,T4240QDS";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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ifc: localbus@ffe124000 {
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reg = <0xf 0xfe124000 0 0x2000>;
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ranges = <0 0 0xf 0xe8000000 0x08000000
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2 0 0xf 0xff800000 0x00010000
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3 0 0xf 0xffdf0000 0x00008000>;
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x8000000>;
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bank-width = <2>;
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device-width = <1>;
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};
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};
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memory {
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device_type = "memory";
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};
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soc: soc@ffe000000 {
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ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
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reg = <0xf 0xfe000000 0 0x00001000>;
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};
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};
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&ifc {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,ifc", "simple-bus";
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interrupts = <25 2 0 0>;
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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soc-sram-error {
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compatible = "fsl,soc-sram-error";
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interrupts = <16 2 1 29>;
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};
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corenet-law@0 {
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compatible = "fsl,corenet-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <32>;
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};
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ddr1: memory-controller@8000 {
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compatible = "fsl,qoriq-memory-controller-v4.7",
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"fsl,qoriq-memory-controller";
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reg = <0x8000 0x1000>;
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interrupts = <16 2 1 23>;
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};
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ddr2: memory-controller@9000 {
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compatible = "fsl,qoriq-memory-controller-v4.7",
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"fsl,qoriq-memory-controller";
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reg = <0x9000 0x1000>;
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interrupts = <16 2 1 22>;
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};
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ddr3: memory-controller@a000 {
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compatible = "fsl,qoriq-memory-controller-v4.7",
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"fsl,qoriq-memory-controller";
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reg = <0xa000 0x1000>;
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interrupts = <16 2 1 21>;
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};
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cpc: l3-cache-controller@10000 {
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compatible = "fsl,t4240-l3-cache-controller", "cache";
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reg = <0x10000 0x1000
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0x11000 0x1000
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0x12000 0x1000>;
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interrupts = <16 2 1 27
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16 2 1 26
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16 2 1 25>;
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};
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corenet-cf@18000 {
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compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
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reg = <0x18000 0x1000>;
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interrupts = <16 2 1 31>;
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fsl,ccf-num-csdids = <32>;
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fsl,ccf-num-snoopids = <32>;
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};
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iommu@20000 {
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compatible = "fsl,pamu-v1.0", "fsl,pamu";
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reg = <0x20000 0x6000>;
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fsl,portid-mapping = <0x8000>;
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interrupts = <
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24 2 0 0
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16 2 1 30>;
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};
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/include/ "fsl/qoriq-mpic.dtsi"
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guts: global-utilities@e0000 {
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compatible = "fsl,t4240-device-config", "fsl,qoriq-device-config-2.0";
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reg = <0xe0000 0xe00>;
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fsl,has-rstcr;
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fsl,liodn-bits = <12>;
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};
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/include/ "fsl/qoriq-clockgen2.dtsi"
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global-utilities@e1000 {
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compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
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};
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/include/ "fsl/qoriq-dma-0.dtsi"
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/include/ "fsl/qoriq-dma-1.dtsi"
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/include/ "fsl/qoriq-i2c-0.dtsi"
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/include/ "fsl/qoriq-i2c-1.dtsi"
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/include/ "fsl/qoriq-duart-0.dtsi"
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/include/ "fsl/qoriq-duart-1.dtsi"
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L2_1: l2-cache-controller@c20000 {
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compatible = "fsl,t4240-l2-cache-controller";
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reg = <0xc20000 0x40000>;
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next-level-cache = <&cpc>;
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};
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L2_2: l2-cache-controller@c60000 {
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compatible = "fsl,t4240-l2-cache-controller";
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reg = <0xc60000 0x40000>;
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next-level-cache = <&cpc>;
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};
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L2_3: l2-cache-controller@ca0000 {
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compatible = "fsl,t4240-l2-cache-controller";
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reg = <0xca0000 0x40000>;
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next-level-cache = <&cpc>;
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};
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};
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