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ARM: imx: Add support for the Armadeus Systems APF51Dev docking board 

The APF51Dev is a docking board for an APF51 SOM

Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Gwenhael Goavec-Merou 2013-03-08 08:41:38 +01:00 committed by Shawn Guo
parent 624dbacace
commit e910b45c9d
2 changed files with 76 additions and 0 deletions
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1
arch/arm/boot/dts/Makefile
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@ -90,6 +90,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx27-pdk.dtb \
imx31-bug.dtb \
imx51-apf51.dtb \
imx51-apf51dev.dtb \
imx51-babbage.dtb \
imx53-ard.dtb \
imx53-evk.dtb \

75
arch/arm/boot/dts/imx51-apf51dev.dts Normal file
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@ -0,0 +1,75 @@
/*
* Copyright 2013 Armadeus Systems - <support@armadeus.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/* APF51Dev is a docking board for the APF51 SOM */
#include "imx51-apf51.dts"
/ {
model = "Armadeus Systems APF51Dev docking/development board";
compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51";
gpio-keys {
compatible = "gpio-keys";
user-key {
label = "user";
gpios = <&gpio1 3 0>;
linux,code = <256>; /* BTN_0 */
};
};
leds {
compatible = "gpio-leds";
user {
label = "Heartbeat";
gpios = <&gpio1 2 0>;
linux,default-trigger = "heartbeat";
};
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
cd-gpios = <&gpio2 29 0>;
bus-width = <4>;
status = "okay";
};
&esdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2_1>;
bus-width = <4>;
non-removable;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
MX51_PAD_EIM_EB2__GPIO2_22 0x0C5
MX51_PAD_EIM_EB3__GPIO2_23 0x0C5
MX51_PAD_EIM_CS4__GPIO2_29 0x100
MX51_PAD_NANDF_D13__GPIO3_27 0x0C5
MX51_PAD_NANDF_D12__GPIO3_28 0x0C5
MX51_PAD_CSPI1_SS0__GPIO4_24 0x0C5
MX51_PAD_CSPI1_SS1__GPIO4_25 0x0C5
MX51_PAD_GPIO1_2__GPIO1_2 0x0C5
MX51_PAD_GPIO1_3__GPIO1_3 0x0C5
>;
};
};
};