clk: sunxi-ng: sun8i: a83t: Use sigma-delta modulation for audio PLL
The audio blocks require specific clock rates. Until now we were using the closest clock rate possible with integer N-M factors. This resulted in audio playback being slightly slower than it should be. The vendor kernel gets around this (for newer SoCs) by using sigma-delta modulation to generate a fractional-N factor. This patch copies the parameters for the A83T. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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@ -76,17 +76,26 @@ static struct ccu_mult pll_c1cpux_clk = {
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*/
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*/
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#define SUN8I_A83T_PLL_AUDIO_REG 0x008
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#define SUN8I_A83T_PLL_AUDIO_REG 0x008
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/* clock rates doubled for post divider */
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static struct ccu_sdm_setting pll_audio_sdm_table[] = {
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{ .rate = 45158400, .pattern = 0xc00121ff, .m = 29, .n = 54 },
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{ .rate = 49152000, .pattern = 0xc000e147, .m = 30, .n = 61 },
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};
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static struct ccu_nm pll_audio_clk = {
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static struct ccu_nm pll_audio_clk = {
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.enable = BIT(31),
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.enable = BIT(31),
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.lock = BIT(2),
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.lock = BIT(2),
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.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
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.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
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.m = _SUNXI_CCU_DIV(0, 6),
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.m = _SUNXI_CCU_DIV(0, 6),
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.fixed_post_div = 2,
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.fixed_post_div = 2,
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.sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, BIT(24),
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0x284, BIT(31)),
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.common = {
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.common = {
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.reg = SUN8I_A83T_PLL_AUDIO_REG,
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.reg = SUN8I_A83T_PLL_AUDIO_REG,
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.lock_reg = CCU_SUN8I_A83T_LOCK_REG,
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.lock_reg = CCU_SUN8I_A83T_LOCK_REG,
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.features = CCU_FEATURE_LOCK_REG |
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.features = CCU_FEATURE_LOCK_REG |
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CCU_FEATURE_FIXED_POSTDIV,
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CCU_FEATURE_FIXED_POSTDIV |
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CCU_FEATURE_SIGMA_DELTA_MOD,
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.hw.init = CLK_HW_INIT("pll-audio", "osc24M",
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.hw.init = CLK_HW_INIT("pll-audio", "osc24M",
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&ccu_nm_ops, CLK_SET_RATE_UNGATE),
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&ccu_nm_ops, CLK_SET_RATE_UNGATE),
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},
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},
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