mtd: spi-nor: Add support for S3AN spi-nor devices
Xilinx Spartan-3AN FPGAs contain an In-System Flash where they keep their configuration data and (optionally) some user data. The protocol of this flash follows most of the spi-nor standard. With the following differences: - Page size might not be a power of two. - The address calculation (default addressing mode). - The spi nor commands used. Protocol is described on Xilinx User Guide UG333 Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
This commit is contained in:
Ricardo Ribalda
Cyrille Pitchen
parent
0cf1725676
commit
e99ca98f1d
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@ -75,6 +75,12 @@ struct flash_info {
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* bit. Must be used with
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* SPI_NOR_HAS_LOCK.
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*/
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#define SPI_S3AN BIT(10) /*
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* Xilinx Spartan 3AN In-System Flash
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* (MFR cannot be used for probing
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* because it has the same value as
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* ATMEL flashes)
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*/
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};
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#define JEDEC_MFR(info) ((info)->id[0])
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@ -217,6 +223,21 @@ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
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return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
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}
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}
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static int s3an_sr_ready(struct spi_nor *nor)
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{
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int ret;
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u8 val;
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ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
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if (ret < 0) {
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dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
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return ret;
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}
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return !!(val & XSR_RDY);
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}
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static inline int spi_nor_sr_ready(struct spi_nor *nor)
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{
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int sr = read_sr(nor);
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@ -238,7 +259,11 @@ static inline int spi_nor_fsr_ready(struct spi_nor *nor)
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static int spi_nor_ready(struct spi_nor *nor)
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{
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int sr, fsr;
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sr = spi_nor_sr_ready(nor);
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if (nor->flags & SNOR_F_READY_XSR_RDY)
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sr = s3an_sr_ready(nor);
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else
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sr = spi_nor_sr_ready(nor);
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if (sr < 0)
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return sr;
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fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
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@ -319,6 +344,24 @@ static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
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mutex_unlock(&nor->lock);
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}
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/*
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* This code converts an address to the Default Address Mode, that has non
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* power of two page sizes. We must support this mode because it is the default
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* mode supported by Xilinx tools, it can access the whole flash area and
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* changing over to the Power-of-two mode is irreversible and corrupts the
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* original data.
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* Addr can safely be unsigned int, the biggest S3AN device is smaller than
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* 4 MiB.
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*/
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static loff_t spi_nor_s3an_addr_convert(struct spi_nor *nor, unsigned int addr)
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{
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unsigned int offset = addr;
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offset %= nor->page_size;
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return ((addr - offset) << 1) | offset;
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}
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/*
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* Initiate the erasure of a single sector
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*/
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@ -327,6 +370,9 @@ static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
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u8 buf[SPI_NOR_MAX_ADDR_WIDTH];
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int i;
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if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
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addr = spi_nor_s3an_addr_convert(nor, addr);
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if (nor->erase)
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return nor->erase(nor, addr);
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@ -368,7 +414,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
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return ret;
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/* whole-chip erase? */
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if (len == mtd->size) {
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if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
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unsigned long timeout;
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write_enable(nor);
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@ -782,6 +828,19 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
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.addr_width = (_addr_width), \
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.flags = (_flags),
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#define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
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.id = { \
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((_jedec_id) >> 16) & 0xff, \
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((_jedec_id) >> 8) & 0xff, \
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(_jedec_id) & 0xff \
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}, \
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.id_len = 3, \
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.sector_size = (8*_page_size), \
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.n_sectors = (_n_sectors), \
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.page_size = _page_size, \
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.addr_width = 3, \
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.flags = SPI_NOR_NO_FR | SPI_S3AN,
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/* NOTE: double check command sets and memory organization when you add
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* more nor chips. This current list focusses on newer chips, which
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* have been converging on command sets which including JEDEC ID.
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@ -1014,6 +1073,13 @@ static const struct flash_info spi_nor_ids[] = {
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{ "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
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{ "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
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{ "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
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/* Xilinx S3AN Internal Flash */
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{ "3S50AN", S3AN_INFO(0x1f2200, 64, 264) },
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{ "3S200AN", S3AN_INFO(0x1f2400, 256, 264) },
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{ "3S400AN", S3AN_INFO(0x1f2400, 256, 264) },
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{ "3S700AN", S3AN_INFO(0x1f2500, 512, 264) },
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{ "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) },
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{ },
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};
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@ -1054,7 +1120,12 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
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return ret;
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while (len) {
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ret = nor->read(nor, from, len, buf);
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loff_t addr = from;
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if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
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addr = spi_nor_s3an_addr_convert(nor, addr);
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ret = nor->read(nor, addr, len, buf);
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if (ret == 0) {
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/* We shouldn't see 0-length reads */
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ret = -EIO;
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@ -1175,8 +1246,23 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
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for (i = 0; i < len; ) {
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ssize_t written;
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loff_t addr = to + i;
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page_offset = (to + i) & (nor->page_size - 1);
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/*
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* If page_size is a power of two, the offset can be quickly
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* calculated with an AND operation. On the other cases we
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* need to do a modulus operation (more expensive).
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* Power of two numbers have only one bit set and we can use
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* the instruction hweight32 to detect if we need to do a
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* modulus (do_div()) or not.
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*/
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if (hweight32(nor->page_size) == 1) {
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page_offset = addr & (nor->page_size - 1);
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} else {
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uint64_t aux = addr;
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page_offset = do_div(aux, nor->page_size);
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}
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WARN_ONCE(page_offset,
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"Writing at offset %zu into a NOR page. Writing partial pages may decrease reliability and increase wear of NOR flash.",
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page_offset);
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@ -1184,8 +1270,11 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
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page_remain = min_t(size_t,
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nor->page_size - page_offset, len - i);
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if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
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addr = spi_nor_s3an_addr_convert(nor, addr);
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write_enable(nor);
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ret = nor->write(nor, to + i, page_remain, buf + i);
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ret = nor->write(nor, addr, page_remain, buf + i);
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if (ret < 0)
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goto write_err;
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written = ret;
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@ -1312,6 +1401,47 @@ static int spi_nor_check(struct spi_nor *nor)
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return 0;
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}
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static int s3an_nor_scan(const struct flash_info *info, struct spi_nor *nor)
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{
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int ret;
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u8 val;
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ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
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if (ret < 0) {
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dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
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return ret;
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}
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nor->erase_opcode = SPINOR_OP_XSE;
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nor->program_opcode = SPINOR_OP_XPP;
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nor->read_opcode = SPINOR_OP_READ;
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nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
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/*
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* This flashes have a page size of 264 or 528 bytes (known as
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* Default addressing mode). It can be changed to a more standard
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* Power of two mode where the page size is 256/512. This comes
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* with a price: there is 3% less of space, the data is corrupted
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* and the page size cannot be changed back to default addressing
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* mode.
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*
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* The current addressing mode can be read from the XRDSR register
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* and should not be changed, because is a destructive operation.
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*/
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if (val & XSR_PAGESIZE) {
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/* Flash in Power of 2 mode */
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nor->page_size = (nor->page_size == 264) ? 256 : 512;
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nor->mtd.writebufsize = nor->page_size;
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nor->mtd.size = 8 * nor->page_size * info->n_sectors;
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nor->mtd.erasesize = 8 * nor->page_size;
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} else {
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/* Flash in Default addressing mode */
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nor->flags |= SNOR_F_S3AN_ADDR_DEFAULT;
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}
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return 0;
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}
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int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
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{
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const struct flash_info *info = NULL;
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@ -1359,6 +1489,14 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
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mutex_init(&nor->lock);
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/*
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* Make sure the XSR_RDY flag is set before calling
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* spi_nor_wait_till_ready(). Xilinx S3AN share MFR
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* with Atmel spi-nor
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*/
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if (info->flags & SPI_S3AN)
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nor->flags |= SNOR_F_READY_XSR_RDY;
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/*
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* Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
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* with the software protection bits set
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@ -1517,6 +1655,12 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
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nor->read_dummy = spi_nor_read_dummy_cycles(nor);
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if (info->flags & SPI_S3AN) {
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ret = s3an_nor_scan(info, nor);
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if (ret)
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return ret;
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}
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dev_info(dev, "%s (%lld Kbytes)\n", info->name,
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(long long)mtd->size >> 10);
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@ -68,6 +68,15 @@
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#define SPINOR_OP_WRDI 0x04 /* Write disable */
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#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
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/* Used for S3AN flashes only */
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#define SPINOR_OP_XSE 0x50 /* Sector erase */
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#define SPINOR_OP_XPP 0x82 /* Page program */
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#define SPINOR_OP_XRDSR 0xd7 /* Read status register */
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#define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
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#define XSR_RDY BIT(7) /* Ready */
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/* Used for Macronix and Winbond flashes. */
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#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
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#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
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@ -119,6 +128,9 @@ enum spi_nor_ops {
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enum spi_nor_option_flags {
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SNOR_F_USE_FSR = BIT(0),
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SNOR_F_HAS_SR_TB = BIT(1),
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SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
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SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
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SNOR_F_READY_XSR_RDY = BIT(4),
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};
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/**
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