ASoC: rt5682: Add CCF usage for providing I2S clks
There is a need to use RT5682 as DAI clock master for other codecs within a platform, which means that the DAI clocks are required to remain, regardless of whether the RT5682 is actually running playback/capture. The RT5682 CCF basic functions are implemented almost by the existing internal functions and asoc apis. It needs a clk provider (rt5682 mclk) to generate the bclk and wclk outputs. The RT5682 CCF supports and restricts as below: 1. Fmt of DAI-AIF1 must be configured to master before using CCF. 2. Only accept a 48MHz clk as the clk provider. 3. Only provide a 48kHz wclk and a set of multiples of wclk as bclk. There are some temporary limitations in this patch until a better implementation. Signed-off-by: Derek Fang <derek.fang@realtek.com> Link: https://lore.kernel.org/r/1582033912-6841-1-git-send-email-derek.fang@realtek.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Derek Fang
Mark Brown
parent
7036810646
commit
ebbfabc16d
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@ -24,6 +24,12 @@ enum rt5682_jd_src {
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RT5682_JD1,
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};
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enum rt5682_dai_clks {
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RT5682_DAI_WCLK_IDX,
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RT5682_DAI_BCLK_IDX,
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RT5682_DAI_NUM_CLKS,
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};
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struct rt5682_platform_data {
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int ldo1_en; /* GPIO for LDO1_EN */
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@ -32,6 +38,8 @@ struct rt5682_platform_data {
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enum rt5682_dmic1_clk_pin dmic1_clk_pin;
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enum rt5682_jd_src jd_src;
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unsigned int btndet_delay;
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const char *dai_clk_names[RT5682_DAI_NUM_CLKS];
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};
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#endif
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@ -27,6 +27,9 @@
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#include <sound/soc-dapm.h>
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#include <sound/initval.h>
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#include <sound/tlv.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <sound/rt5682.h>
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#include "rl6231.h"
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@ -45,6 +48,8 @@ static const struct rt5682_platform_data i2s_default_platform_data = {
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.dmic1_clk_pin = RT5682_DMIC1_CLK_GPIO3,
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.jd_src = RT5682_JD1,
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.btndet_delay = 16,
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.dai_clk_names[RT5682_DAI_WCLK_IDX] = "rt5682-dai-wclk",
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.dai_clk_names[RT5682_DAI_BCLK_IDX] = "rt5682-dai-bclk",
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};
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struct rt5682_priv {
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@ -58,6 +63,13 @@ struct rt5682_priv {
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struct mutex calibrate_mutex;
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bool is_sdw;
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#ifdef CONFIG_COMMON_CLK
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struct clk_hw dai_clks_hw[RT5682_DAI_NUM_CLKS];
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struct clk_lookup *dai_clks_lookup[RT5682_DAI_NUM_CLKS];
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struct clk *dai_clks[RT5682_DAI_NUM_CLKS];
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struct clk *mclk;
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#endif
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int sysclk;
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int sysclk_src;
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int lrck[RT5682_AIFS];
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@ -921,6 +933,7 @@ static int rt5682_headset_detect(struct snd_soc_component *component,
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int jack_insert)
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{
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struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
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struct snd_soc_dapm_context *dapm = &component->dapm;
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unsigned int val, count;
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if (jack_insert) {
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@ -963,7 +976,12 @@ static int rt5682_headset_detect(struct snd_soc_component *component,
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rt5682_enable_push_button_irq(component, false);
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snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
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RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
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snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
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if (snd_soc_dapm_get_pin_status(dapm, "MICBIAS"))
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snd_soc_component_update_bits(component,
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RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
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else
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snd_soc_component_update_bits(component,
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RT5682_PWR_ANLG_1,
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RT5682_PWR_VREF2 | RT5682_PWR_MB, 0);
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snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
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RT5682_PWR_CBJ, 0);
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@ -1633,6 +1651,7 @@ static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
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rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
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SND_SOC_DAPM_SUPPLY("Vref2", RT5682_PWR_ANLG_1, RT5682_PWR_VREF2_BIT, 0,
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NULL, 0),
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SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0),
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/* ASRC */
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SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
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@ -2459,12 +2478,380 @@ static int rt5682_set_bias_level(struct snd_soc_component *component,
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return 0;
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}
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#ifdef CONFIG_COMMON_CLK
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#define CLK_PLL2_FIN 48000000
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#define CLK_PLL2_FOUT 24576000
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#define CLK_48 48000
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static bool rt5682_clk_check(struct rt5682_priv *rt5682)
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{
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if (!rt5682->master[RT5682_AIF1]) {
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dev_err(rt5682->component->dev, "sysclk/dai not set correctly\n");
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return false;
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}
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return true;
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}
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static int rt5682_wclk_prepare(struct clk_hw *hw)
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{
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struct rt5682_priv *rt5682 =
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container_of(hw, struct rt5682_priv,
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dai_clks_hw[RT5682_DAI_WCLK_IDX]);
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struct snd_soc_component *component = rt5682->component;
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struct snd_soc_dapm_context *dapm =
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snd_soc_component_get_dapm(component);
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if (!rt5682_clk_check(rt5682))
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return -EINVAL;
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snd_soc_dapm_mutex_lock(dapm);
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snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
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snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
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RT5682_PWR_MB, RT5682_PWR_MB);
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snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1");
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snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F");
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snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B");
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snd_soc_dapm_sync_unlocked(dapm);
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snd_soc_dapm_mutex_unlock(dapm);
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return 0;
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}
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static void rt5682_wclk_unprepare(struct clk_hw *hw)
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{
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struct rt5682_priv *rt5682 =
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container_of(hw, struct rt5682_priv,
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dai_clks_hw[RT5682_DAI_WCLK_IDX]);
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struct snd_soc_component *component = rt5682->component;
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struct snd_soc_dapm_context *dapm =
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snd_soc_component_get_dapm(component);
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if (!rt5682_clk_check(rt5682))
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return;
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snd_soc_dapm_mutex_lock(dapm);
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snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
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if (!rt5682->jack_type)
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snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
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RT5682_PWR_MB, 0);
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snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1");
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snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F");
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snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B");
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snd_soc_dapm_sync_unlocked(dapm);
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snd_soc_dapm_mutex_unlock(dapm);
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}
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static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct rt5682_priv *rt5682 =
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container_of(hw, struct rt5682_priv,
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dai_clks_hw[RT5682_DAI_WCLK_IDX]);
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if (!rt5682_clk_check(rt5682))
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return 0;
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/*
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* Only accept to set wclk rate to 48kHz temporarily.
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*/
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return CLK_48;
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}
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static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct rt5682_priv *rt5682 =
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container_of(hw, struct rt5682_priv,
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dai_clks_hw[RT5682_DAI_WCLK_IDX]);
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if (!rt5682_clk_check(rt5682))
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return -EINVAL;
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/*
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* Only accept to set wclk rate to 48kHz temporarily.
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*/
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return CLK_48;
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}
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static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct rt5682_priv *rt5682 =
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container_of(hw, struct rt5682_priv,
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dai_clks_hw[RT5682_DAI_WCLK_IDX]);
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struct snd_soc_component *component = rt5682->component;
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struct clk *parent_clk;
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const char * const clk_name = __clk_get_name(hw->clk);
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int pre_div;
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if (!rt5682_clk_check(rt5682))
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return -EINVAL;
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/*
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* Whether the wclk's parent clk (mclk) exists or not, please ensure
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* it is fixed or set to 48MHz before setting wclk rate. It's a
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* temporary limitation. Only accept 48MHz clk as the clk provider.
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*
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* It will set the codec anyway by assuming mclk is 48MHz.
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*/
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parent_clk = clk_get_parent(hw->clk);
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if (!parent_clk)
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dev_warn(component->dev,
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"Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
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CLK_PLL2_FIN);
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if (parent_rate != CLK_PLL2_FIN)
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dev_warn(component->dev, "clk %s only support %d Hz input\n",
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clk_name, CLK_PLL2_FIN);
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/*
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* It's a temporary limitation. Only accept to set wclk rate to 48kHz.
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* It will force wclk to 48kHz even it's not.
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*/
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if (rate != CLK_48) {
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dev_warn(component->dev, "clk %s only support %d Hz output\n",
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clk_name, CLK_48);
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rate = CLK_48;
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}
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/*
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* To achieve the rate conversion from 48MHz to 48kHz, PLL2 is needed.
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*/
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rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK,
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CLK_PLL2_FIN, CLK_PLL2_FOUT);
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rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0,
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CLK_PLL2_FOUT, SND_SOC_CLOCK_IN);
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pre_div = rl6231_get_clk_info(rt5682->sysclk, rate);
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snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
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RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK,
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pre_div << RT5682_I2S_M_DIV_SFT |
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(rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
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return 0;
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}
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static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct rt5682_priv *rt5682 =
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container_of(hw, struct rt5682_priv,
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dai_clks_hw[RT5682_DAI_BCLK_IDX]);
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struct snd_soc_component *component = rt5682->component;
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unsigned int bclks_per_wclk;
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snd_soc_component_read(component, RT5682_TDM_TCON_CTRL,
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&bclks_per_wclk);
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switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) {
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case RT5682_TDM_BCLK_MS1_256:
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return parent_rate * 256;
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case RT5682_TDM_BCLK_MS1_128:
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return parent_rate * 128;
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case RT5682_TDM_BCLK_MS1_64:
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return parent_rate * 64;
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case RT5682_TDM_BCLK_MS1_32:
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return parent_rate * 32;
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default:
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return 0;
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}
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}
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static unsigned long rt5682_bclk_get_factor(unsigned long rate,
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unsigned long parent_rate)
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{
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unsigned long factor;
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factor = rate / parent_rate;
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if (factor < 64)
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return 32;
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else if (factor < 128)
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return 64;
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else if (factor < 256)
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return 128;
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else
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return 256;
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}
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static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct rt5682_priv *rt5682 =
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container_of(hw, struct rt5682_priv,
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dai_clks_hw[RT5682_DAI_BCLK_IDX]);
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unsigned long factor;
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if (!*parent_rate || !rt5682_clk_check(rt5682))
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return -EINVAL;
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/*
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* BCLK rates are set as a multiplier of WCLK in HW.
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* We don't allow changing the parent WCLK. We just do
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* some rounding down based on the parent WCLK rate
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* and find the appropriate multiplier of BCLK to
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* get the rounded down BCLK value.
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*/
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factor = rt5682_bclk_get_factor(rate, *parent_rate);
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return *parent_rate * factor;
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}
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static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct rt5682_priv *rt5682 =
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container_of(hw, struct rt5682_priv,
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dai_clks_hw[RT5682_DAI_BCLK_IDX]);
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struct snd_soc_component *component = rt5682->component;
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struct snd_soc_dai *dai = NULL;
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unsigned long factor;
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if (!rt5682_clk_check(rt5682))
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return -EINVAL;
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factor = rt5682_bclk_get_factor(rate, parent_rate);
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for_each_component_dais(component, dai)
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if (dai->id == RT5682_AIF1)
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break;
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if (!dai) {
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dev_err(component->dev, "dai %d not found in component\n",
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RT5682_AIF1);
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return -ENODEV;
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}
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return rt5682_set_bclk1_ratio(dai, factor);
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}
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static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = {
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[RT5682_DAI_WCLK_IDX] = {
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.prepare = rt5682_wclk_prepare,
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.unprepare = rt5682_wclk_unprepare,
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.recalc_rate = rt5682_wclk_recalc_rate,
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.round_rate = rt5682_wclk_round_rate,
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.set_rate = rt5682_wclk_set_rate,
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},
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[RT5682_DAI_BCLK_IDX] = {
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.recalc_rate = rt5682_bclk_recalc_rate,
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.round_rate = rt5682_bclk_round_rate,
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.set_rate = rt5682_bclk_set_rate,
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},
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};
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static int rt5682_register_dai_clks(struct snd_soc_component *component)
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{
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struct device *dev = component->dev;
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struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
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struct rt5682_platform_data *pdata = &rt5682->pdata;
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struct clk_init_data init;
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struct clk *dai_clk;
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struct clk_lookup *dai_clk_lookup;
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struct clk_hw *dai_clk_hw;
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const char *parent_name;
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int i, ret;
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for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) {
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dai_clk_hw = &rt5682->dai_clks_hw[i];
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switch (i) {
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case RT5682_DAI_WCLK_IDX:
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/* Make MCLK the parent of WCLK */
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if (rt5682->mclk) {
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parent_name = __clk_get_name(rt5682->mclk);
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init.parent_names = &parent_name;
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init.num_parents = 1;
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} else {
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init.parent_names = NULL;
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init.num_parents = 0;
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}
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break;
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case RT5682_DAI_BCLK_IDX:
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/* Make WCLK the parent of BCLK */
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parent_name = __clk_get_name(
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rt5682->dai_clks[RT5682_DAI_WCLK_IDX]);
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init.parent_names = &parent_name;
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init.num_parents = 1;
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break;
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default:
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dev_err(dev, "Invalid clock index\n");
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ret = -EINVAL;
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goto err;
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}
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init.name = pdata->dai_clk_names[i];
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init.ops = &rt5682_dai_clk_ops[i];
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init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
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dai_clk_hw->init = &init;
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dai_clk = devm_clk_register(dev, dai_clk_hw);
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if (IS_ERR(dai_clk)) {
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dev_warn(dev, "Failed to register %s: %ld\n",
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init.name, PTR_ERR(dai_clk));
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ret = PTR_ERR(dai_clk);
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goto err;
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}
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||||
rt5682->dai_clks[i] = dai_clk;
|
||||
|
||||
if (dev->of_node) {
|
||||
devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
|
||||
dai_clk_hw);
|
||||
} else {
|
||||
dai_clk_lookup = clkdev_create(dai_clk, init.name,
|
||||
"%s", dev_name(dev));
|
||||
if (!dai_clk_lookup) {
|
||||
ret = -ENOMEM;
|
||||
goto err;
|
||||
} else {
|
||||
rt5682->dai_clks_lookup[i] = dai_clk_lookup;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
do {
|
||||
if (rt5682->dai_clks_lookup[i])
|
||||
clkdev_drop(rt5682->dai_clks_lookup[i]);
|
||||
} while (i-- > 0);
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif /* CONFIG_COMMON_CLK */
|
||||
|
||||
static int rt5682_probe(struct snd_soc_component *component)
|
||||
{
|
||||
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
|
||||
|
||||
#ifdef CONFIG_COMMON_CLK
|
||||
int ret;
|
||||
#endif
|
||||
rt5682->component = component;
|
||||
|
||||
#ifdef CONFIG_COMMON_CLK
|
||||
/* Check if MCLK provided */
|
||||
rt5682->mclk = devm_clk_get(component->dev, "mclk");
|
||||
if (IS_ERR(rt5682->mclk)) {
|
||||
if (PTR_ERR(rt5682->mclk) != -ENOENT) {
|
||||
ret = PTR_ERR(rt5682->mclk);
|
||||
return ret;
|
||||
}
|
||||
rt5682->mclk = NULL;
|
||||
}
|
||||
|
||||
/* Register CCF DAI clock control */
|
||||
ret = rt5682_register_dai_clks(component);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Initial setup for CCF */
|
||||
rt5682->lrck[RT5682_AIF1] = CLK_48;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -2472,6 +2859,15 @@ static void rt5682_remove(struct snd_soc_component *component)
|
|||
{
|
||||
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
|
||||
|
||||
#ifdef CONFIG_COMMON_CLK
|
||||
int i;
|
||||
|
||||
for (i = RT5682_DAI_NUM_CLKS - 1; i >= 0; --i) {
|
||||
if (rt5682->dai_clks_lookup[i])
|
||||
clkdev_drop(rt5682->dai_clks_lookup[i]);
|
||||
}
|
||||
#endif
|
||||
|
||||
rt5682_reset(rt5682);
|
||||
}
|
||||
|
||||
|
|
@ -2606,6 +3002,13 @@ static int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
|
|||
rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
|
||||
"realtek,ldo1-en-gpios", 0);
|
||||
|
||||
if (device_property_read_string_array(dev, "clock-output-names",
|
||||
rt5682->pdata.dai_clk_names,
|
||||
RT5682_DAI_NUM_CLKS) < 0)
|
||||
dev_warn(dev, "Using default DAI clk names: %s, %s\n",
|
||||
rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX],
|
||||
rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -841,8 +841,8 @@
|
|||
#define RT5682_TDM_M_LP_INV (0x1 << 1)
|
||||
#define RT5682_TDM_MS_MASK (0x1 << 0)
|
||||
#define RT5682_TDM_MS_SFT 0
|
||||
#define RT5682_TDM_MS_M (0x0 << 0)
|
||||
#define RT5682_TDM_MS_S (0x1 << 0)
|
||||
#define RT5682_TDM_MS_S (0x0 << 0)
|
||||
#define RT5682_TDM_MS_M (0x1 << 0)
|
||||
|
||||
/* Global Clock Control (0x0080) */
|
||||
#define RT5682_SCLK_SRC_MASK (0x7 << 13)
|
||||
|
|
|
|||
Loading…
Reference in New Issue