drm/g94-/disp: add method to power-off dp lanes
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
55f083c33f
commit
ebd6acbb06
|
@ -77,6 +77,7 @@ nv94_disp_base_omthds[] = {
|
||||||
{ SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd },
|
{ SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd },
|
||||||
{ SOR_MTHD(NV84_DISP_SOR_HDMI_PWR) , nv50_sor_mthd },
|
{ SOR_MTHD(NV84_DISP_SOR_HDMI_PWR) , nv50_sor_mthd },
|
||||||
{ SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
|
{ SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
|
||||||
|
{ SOR_MTHD(NV94_DISP_SOR_DP_PWR) , nv50_sor_mthd },
|
||||||
{ DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd },
|
{ DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd },
|
||||||
{ DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd },
|
{ DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd },
|
||||||
{ PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd },
|
{ PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd },
|
||||||
|
|
|
@ -50,6 +50,7 @@ nva3_disp_base_omthds[] = {
|
||||||
{ SOR_MTHD(NVA3_DISP_SOR_HDA_ELD) , nv50_sor_mthd },
|
{ SOR_MTHD(NVA3_DISP_SOR_HDA_ELD) , nv50_sor_mthd },
|
||||||
{ SOR_MTHD(NV84_DISP_SOR_HDMI_PWR) , nv50_sor_mthd },
|
{ SOR_MTHD(NV84_DISP_SOR_HDMI_PWR) , nv50_sor_mthd },
|
||||||
{ SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
|
{ SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
|
||||||
|
{ SOR_MTHD(NV94_DISP_SOR_DP_PWR) , nv50_sor_mthd },
|
||||||
{ DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd },
|
{ DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd },
|
||||||
{ DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd },
|
{ DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd },
|
||||||
{ PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd },
|
{ PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd },
|
||||||
|
|
|
@ -887,6 +887,7 @@ nvd0_disp_base_omthds[] = {
|
||||||
{ SOR_MTHD(NVA3_DISP_SOR_HDA_ELD) , nv50_sor_mthd },
|
{ SOR_MTHD(NVA3_DISP_SOR_HDA_ELD) , nv50_sor_mthd },
|
||||||
{ SOR_MTHD(NV84_DISP_SOR_HDMI_PWR) , nv50_sor_mthd },
|
{ SOR_MTHD(NV84_DISP_SOR_HDMI_PWR) , nv50_sor_mthd },
|
||||||
{ SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
|
{ SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
|
||||||
|
{ SOR_MTHD(NV94_DISP_SOR_DP_PWR) , nv50_sor_mthd },
|
||||||
{ DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd },
|
{ DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd },
|
||||||
{ DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd },
|
{ DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd },
|
||||||
{ PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd },
|
{ PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd },
|
||||||
|
|
|
@ -47,8 +47,12 @@ int
|
||||||
nv50_sor_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size)
|
nv50_sor_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size)
|
||||||
{
|
{
|
||||||
struct nv50_disp_priv *priv = (void *)object->engine;
|
struct nv50_disp_priv *priv = (void *)object->engine;
|
||||||
|
const u8 type = (mthd & NV50_DISP_SOR_MTHD_TYPE) >> 12;
|
||||||
const u8 head = (mthd & NV50_DISP_SOR_MTHD_HEAD) >> 3;
|
const u8 head = (mthd & NV50_DISP_SOR_MTHD_HEAD) >> 3;
|
||||||
|
const u8 link = (mthd & NV50_DISP_SOR_MTHD_LINK) >> 2;
|
||||||
const u8 or = (mthd & NV50_DISP_SOR_MTHD_OR);
|
const u8 or = (mthd & NV50_DISP_SOR_MTHD_OR);
|
||||||
|
const u16 mask = (0x0100 << head) | (0x0040 << link) | (0x0001 << or);
|
||||||
|
struct nvkm_output *outp = NULL, *temp;
|
||||||
u32 data;
|
u32 data;
|
||||||
int ret = -EINVAL;
|
int ret = -EINVAL;
|
||||||
|
|
||||||
|
@ -56,6 +60,13 @@ nv50_sor_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
data = *(u32 *)args;
|
data = *(u32 *)args;
|
||||||
|
|
||||||
|
list_for_each_entry(temp, &priv->base.outp, head) {
|
||||||
|
if ((temp->info.hasht & 0xff) == type &&
|
||||||
|
(temp->info.hashm & mask) == mask) {
|
||||||
|
outp = temp;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
switch (mthd & ~0x3f) {
|
switch (mthd & ~0x3f) {
|
||||||
case NV50_DISP_SOR_PWR:
|
case NV50_DISP_SOR_PWR:
|
||||||
|
@ -71,6 +82,23 @@ nv50_sor_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size)
|
||||||
priv->sor.lvdsconf = data & NV50_DISP_SOR_LVDS_SCRIPT_ID;
|
priv->sor.lvdsconf = data & NV50_DISP_SOR_LVDS_SCRIPT_ID;
|
||||||
ret = 0;
|
ret = 0;
|
||||||
break;
|
break;
|
||||||
|
case NV94_DISP_SOR_DP_PWR:
|
||||||
|
if (outp) {
|
||||||
|
struct nvkm_output_dp *outpdp = (void *)outp;
|
||||||
|
switch (data) {
|
||||||
|
case NV94_DISP_SOR_DP_PWR_STATE_OFF:
|
||||||
|
((struct nvkm_output_dp_impl *)nv_oclass(outp))
|
||||||
|
->lnk_pwr(outpdp, 0);
|
||||||
|
atomic_set(&outpdp->lt.done, 0);
|
||||||
|
break;
|
||||||
|
case NV94_DISP_SOR_DP_PWR_STATE_ON:
|
||||||
|
nvkm_output_dp_train(&outpdp->base, 0, true);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
break;
|
||||||
default:
|
default:
|
||||||
BUG_ON(1);
|
BUG_ON(1);
|
||||||
}
|
}
|
||||||
|
|
|
@ -295,6 +295,10 @@ struct nv04_display_scanoutpos {
|
||||||
#define NV84_DISP_SOR_HDMI_PWR_REKEY 0x0000007f
|
#define NV84_DISP_SOR_HDMI_PWR_REKEY 0x0000007f
|
||||||
#define NV50_DISP_SOR_LVDS_SCRIPT 0x00013000
|
#define NV50_DISP_SOR_LVDS_SCRIPT 0x00013000
|
||||||
#define NV50_DISP_SOR_LVDS_SCRIPT_ID 0x0000ffff
|
#define NV50_DISP_SOR_LVDS_SCRIPT_ID 0x0000ffff
|
||||||
|
#define NV94_DISP_SOR_DP_PWR 0x00016000
|
||||||
|
#define NV94_DISP_SOR_DP_PWR_STATE 0x00000001
|
||||||
|
#define NV94_DISP_SOR_DP_PWR_STATE_OFF 0x00000000
|
||||||
|
#define NV94_DISP_SOR_DP_PWR_STATE_ON 0x00000001
|
||||||
|
|
||||||
#define NV50_DISP_DAC_MTHD 0x00020000
|
#define NV50_DISP_DAC_MTHD 0x00020000
|
||||||
#define NV50_DISP_DAC_MTHD_TYPE 0x0000f000
|
#define NV50_DISP_DAC_MTHD_TYPE 0x0000f000
|
||||||
|
|
Loading…
Reference in New Issue