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drm/i915/glk: Validate only DSI PORT A PLL divider 

As per BSPEC, GLK supports MIPI DSI 8X clk only on PORT A.
Therefore only for PORT A PLL divider value should be validated.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1487335415-14766-8-git-send-email-madhav.chauhan@intel.com
This commit is contained in:
Madhav Chauhan 2017-02-17 18:13:35 +05:30 committed by Jani Nikula
parent bcc6570048
commit ebeac38025
1 changed files with 13 additions and 6 deletions
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19
drivers/gpu/drm/i915/intel_dsi_pll.c
View File

@ -206,17 +206,24 @@ static bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
return false;
/*
* Both dividers must be programmed with valid values even if only one
* of the PLL is used, see BSpec/Broxton Clocks. Check this here for
* Dividers must be programmed with valid values. As per BSEPC, for
* GEMINLAKE only PORT A divider values are checked while for BXT
* both divider values are validated. Check this here for
* paranoia, since BIOS is known to misconfigure PLLs in this way at
* times, and since accessing DSI registers with invalid dividers
* causes a system hang.
*/
val = I915_READ(BXT_DSI_PLL_CTL);
if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) {
DRM_DEBUG_DRIVER("PLL is enabled with invalid divider settings (%08x)\n",
val);
enabled = false;
if (IS_GEMINILAKE(dev_priv)) {
if (!(val & BXT_DSIA_16X_MASK)) {
DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val);
enabled = false;
}
} else {
if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) {
DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val);
enabled = false;
}
}
return enabled;