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mvebu fixes for 4.7 (part 1) 

Various I/O memory fix for Cortex A9 based SoCs
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Merge tag 'mvebu-fixes-4.7-1' of git://git.infradead.org/linux-mvebu into fixes

mvebu fixes for 4.7 (part 1)

Various I/O memory fix for Cortex A9 based SoCs

* tag 'mvebu-fixes-4.7-1' of git://git.infradead.org/linux-mvebu:
  ARM: dts: armada-38x: fix MBUS_ID for crypto SRAM on Armada 385 Linksys
  ARM: mvebu: map PCI I/O regions strongly ordered
  ARM: mvebu: fix HW I/O coherency related deadlocks

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2016-06-25 21:19:37 -07:00
parent 33688abb28 929e604efa
commit ed749a53b2
2 changed files with 11 additions and 16 deletions
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4
arch/arm/boot/dts/armada-385-linksys.dtsi
View File

@ -58,8 +58,8 @@ memory {
soc { soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>; MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
internal-regs { internal-regs {

23
arch/arm/mach-mvebu/coherency.c
View File

@ -162,22 +162,16 @@ static void __init armada_370_coherency_init(struct device_node *np)
} }
/* /*
* This ioremap hook is used on Armada 375/38x to ensure that PCIe * This ioremap hook is used on Armada 375/38x to ensure that all MMIO
* memory areas are mapped as MT_UNCACHED instead of MT_DEVICE. This * areas are mapped as MT_UNCACHED instead of MT_DEVICE. This is
* is needed as a workaround for a deadlock issue between the PCIe * needed for the HW I/O coherency mechanism to work properly without
* interface and the cache controller. * deadlock.
*/ */
static void __iomem * static void __iomem *
armada_pcie_wa_ioremap_caller(phys_addr_t phys_addr, size_t size, armada_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
unsigned int mtype, void *caller) unsigned int mtype, void *caller)
{ {
struct resource pcie_mem; mtype = MT_UNCACHED;
mvebu_mbus_get_pcie_mem_aperture(&pcie_mem);
if (pcie_mem.start <= phys_addr && (phys_addr + size) <= pcie_mem.end)
mtype = MT_UNCACHED;
return __arm_ioremap_caller(phys_addr, size, mtype, caller); return __arm_ioremap_caller(phys_addr, size, mtype, caller);
} }
@ -186,7 +180,8 @@ static void __init armada_375_380_coherency_init(struct device_node *np)
struct device_node *cache_dn; struct device_node *cache_dn;
coherency_cpu_base = of_iomap(np, 0); coherency_cpu_base = of_iomap(np, 0);
arch_ioremap_caller = armada_pcie_wa_ioremap_caller; arch_ioremap_caller = armada_wa_ioremap_caller;
pci_ioremap_set_mem_type(MT_UNCACHED);
/* /*
* We should switch the PL310 to I/O coherency mode only if * We should switch the PL310 to I/O coherency mode only if