dt-bindings: add binding for the Allwinner DE2 CCU
Allwinner "Display Engine 2.0" contains some clock controls in it. In order to add them as clock drivers, we need a device tree binding. Add the binding here. Also add the device tree binding headers. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Allwinner Display Engine 2.0 Clock Control Binding
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--------------------------------------------------
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Required properties :
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- compatible: must contain one of the following compatibles:
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- "allwinner,sun8i-a83t-de2-clk"
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- "allwinner,sun8i-v3s-de2-clk"
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- "allwinner,sun50i-h5-de2-clk"
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- reg: Must contain the registers base address and length
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- clocks: phandle to the clocks feeding the display engine subsystem.
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Three are needed:
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- "mod": the display engine module clock
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- "bus": the bus clock for the whole display engine subsystem
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- clock-names: Must contain the clock names described just above
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- resets: phandle to the reset control for the display engine subsystem.
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- #clock-cells : must contain 1
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- #reset-cells : must contain 1
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Example:
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de2_clocks: clock@1000000 {
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compatible = "allwinner,sun8i-a83t-de2-clk";
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reg = <0x01000000 0x100000>;
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clocks = <&ccu CLK_BUS_DE>,
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<&ccu CLK_DE>;
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clock-names = "bus",
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"mod";
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resets = <&ccu RST_BUS_DE>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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/*
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* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.io>
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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#ifndef _DT_BINDINGS_CLOCK_SUN8I_DE2_H_
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#define _DT_BINDINGS_CLOCK_SUN8I_DE2_H_
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#define CLK_BUS_MIXER0 0
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#define CLK_BUS_MIXER1 1
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#define CLK_BUS_WB 2
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#define CLK_MIXER0 6
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#define CLK_MIXER1 7
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#define CLK_WB 8
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#endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */
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/*
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* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.io>
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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#ifndef _DT_BINDINGS_RESET_SUN8I_DE2_H_
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#define _DT_BINDINGS_RESET_SUN8I_DE2_H_
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#define RST_MIXER0 0
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#define RST_MIXER1 1
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#define RST_WB 2
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#endif /* _DT_BINDINGS_RESET_SUN8I_DE2_H_ */
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