Bitmain SoC changes for v5.1:
- Document Bitmain BM1880 SoC bindings - Add ARCH_BITMAIN for supporting Bitmain SoC platforms - Add devicetree support for Bitmain BM1880 SoC - Add devicetree support for Sophon Edge board - Add MAINTAINERS entry for Bitmain SoC platform -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEZ6VDKoFIy9ikWCeXVZ8R5v6RzvUFAlxes/cACgkQVZ8R5v6R zvXU6wf/cJxHGTZGs/kTpV217G1RzG7LN6YAYyl9707d61Vk9va+0NiV2W32+0w2 EqDARP09SzeFLIjQ275CLzAqqQC4hnnuB0hF4ZwBMXtDGlohaBmfVu3+B8SxqVDE d0Y+wuGtO4MRe5HfClayfvVf3kx6SjQY5C7bJz2RJVf69QCZK2q+a9R21cckMkEb 4EBvgId0FoIIkZJ0CYLN1T4u1i0zpTBfCEmpkInmbdcjMBlZS4+BCwR+KuM6Lwns 7UUF0eBAhFN/A23W9+7VT9CZi3n6ipRSCx0dUXXEUEst0yr3YWhsnWaS88UOGbDD xiKRl8+C7/uO1kUZ9cxQoPWlYRVqlQ== =W7/m -----END PGP SIGNATURE----- Merge tag 'bitmain-initial-soc-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-bitmain into arm/newsoc Bitmain SoC changes for v5.1: - Document Bitmain BM1880 SoC bindings - Add ARCH_BITMAIN for supporting Bitmain SoC platforms - Add devicetree support for Bitmain BM1880 SoC - Add devicetree support for Sophon Edge board - Add MAINTAINERS entry for Bitmain SoC platform * tag 'bitmain-initial-soc-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-bitmain: MAINTAINERS: Add entry for Bitmain SoC platform arm64: dts: bitmain: Add Sophon Egde board support arm64: dts: bitmain: Add BM1880 SoC support arm64: Add ARCH_BITMAIN platform dt-bindings: arm: Document Bitmain BM1880 SoC Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
ee036df9bd
|
|
@ -0,0 +1,18 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/bitmain.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Bitmain platform device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- bitmain,sophon-edge
|
||||
- const: bitmain,bm1880
|
||||
...
|
||||
|
|
@ -1372,6 +1372,13 @@ F: arch/arm/mach-aspeed/
|
|||
F: arch/arm/boot/dts/aspeed-*
|
||||
N: aspeed
|
||||
|
||||
ARM/BITMAIN ARCHITECTURE
|
||||
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm64/boot/dts/bitmain/
|
||||
F: Documentation/devicetree/bindings/arm/bitmain.yaml
|
||||
|
||||
ARM/CALXEDA HIGHBANK ARCHITECTURE
|
||||
M: Rob Herring <robh@kernel.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
|
|
|
|||
|
|
@ -52,6 +52,11 @@ config ARCH_BERLIN
|
|||
help
|
||||
This enables support for Marvell Berlin SoC Family
|
||||
|
||||
config ARCH_BITMAIN
|
||||
bool "Bitmain SoC Platforms"
|
||||
help
|
||||
This enables support for the Bitmain SoC Family.
|
||||
|
||||
config ARCH_BRCMSTB
|
||||
bool "Broadcom Set-Top-Box SoCs"
|
||||
select BRCMSTB_L2_IRQ
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ subdir-y += amd
|
|||
subdir-y += amlogic
|
||||
subdir-y += apm
|
||||
subdir-y += arm
|
||||
subdir-y += bitmain
|
||||
subdir-y += broadcom
|
||||
subdir-y += cavium
|
||||
subdir-y += exynos
|
||||
|
|
|
|||
|
|
@ -0,0 +1,3 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
dtb-$(CONFIG_ARCH_BITMAIN) += bm1880-sophon-edge.dtb
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 Linaro Ltd.
|
||||
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bm1880.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "bitmain,sophon-edge", "bitmain,bm1880";
|
||||
model = "Sophon Edge";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x1 0x00000000 0x0 0x40000000>; // 1GB
|
||||
};
|
||||
|
||||
uart_clk: uart-clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <500000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
clocks = <&uart_clk>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
clocks = <&uart_clk>;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
clocks = <&uart_clk>;
|
||||
};
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 Linaro Ltd.
|
||||
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "bitmain,bm1880";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secmon@100000000 {
|
||||
reg = <0x1 0x00000000 0x0 0x20000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
jpu@130000000 {
|
||||
reg = <0x1 0x30000000 0x0 0x08000000>; // 128M
|
||||
no-map;
|
||||
};
|
||||
|
||||
vpu@138000000 {
|
||||
reg = <0x1 0x38000000 0x0 0x08000000>; // 128M
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
gic: interrupt-controller@50001000 {
|
||||
compatible = "arm,gic-400";
|
||||
reg = <0x0 0x50001000 0x0 0x1000>,
|
||||
<0x0 0x50002000 0x0 0x2000>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
};
|
||||
|
||||
uart0: serial@58018000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x58018000 0x0 0x2000>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@5801A000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x5801a000 0x0 0x2000>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@5801C000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x5801c000 0x0 0x2000>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@5801E000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x5801e000 0x0 0x2000>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue