Qualcomm ARM64 Updates for v4.4
* Add RNG device tree node * Add MSM8x16 serial UART1 node * Enable eMMC on apq8016-sbc board * Fix I2C pinconf sleep state function * Add MSM8916 I2C nodes * Enable I2C busses on LS and HS on APQ8016-sbc * Enable SPI busses on LS and HS on APQ8016-sbc -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJWHcRMAAoJEFKiBbHx2RXVNzYP/19jGaB621TS81MhbUPARaTj AsZCGy+YOejlBd7kCbBm7tSVlNQ1CRi1iESnhIzYptvpOz4Net2gpT66pexrJHag 2wvbk1zUepl3cNwOLHjFSBBf+6cmgS9Hy57vdGM5ucqre60LemDAj1okV0CMxGOt REv+MjGWrWgz99qvJ8w1zPxDUDunH/94uqGXV5k19ziH8QqhoCvTdeshmYLy2lsa jmxPww9jCxsLDLlMWIH2k4toSOUzZcmr2N4R1e/HRcSlgTBLcwrlGDqO5wIwVw5m eTmKCryndrYEx8AzafHNfEWD3AX0rIgD3MfgMDpuVy6s8R0Lgl86ewmeYLj+1TcF Vtu9PKQ2VDAXC6m883TIWnT1yV+ggXOrK/8VQWu4YVFToBTAEUNYnuQ6b8+sig3J 7KvUY6PEsGF3uldTx7prnhXsBd/2gDTxnFgcGq44ZdyEKdPuL6iJxUfbkJ2hzVhR Qh7kqf8WHTHCPFPjp52L+8AKxpCRJGJBKTZYm+yYeAPEEZzFWCEfnzVsQzZiEt1M /6lojXSv5SNR0NezAvFGbELJrTEbBglYp+VfcO8gOm3xfvyRwL9JF/7LtWdIpFa5 LGxDXpxgSFQYnQAwKQtqT39aWVQIicOID5EeuXUxXBd30uBsfGKJAPN8x6z/YLiQ rhgbXuIMDFoweMJPCWHE =pMvh -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-for-4.4' of git://codeaurora.org/quic/kernel/agross-msm into next/dt Pull "Qualcomm ARM64 Updates for v4.4" from Andy Gross: * Add RNG device tree node * Add MSM8x16 serial UART1 node * Enable eMMC on apq8016-sbc board * Fix I2C pinconf sleep state function * Add MSM8916 I2C nodes * Enable I2C busses on LS and HS on APQ8016-sbc * Enable SPI busses on LS and HS on APQ8016-sbc * tag 'qcom-arm64-for-4.4' of git://codeaurora.org/quic/kernel/agross-msm: arm64: dts: apq8016-sbc: enable spi buses on LS and HS arm64: dts: apq8016-sbc: enable i2c buses on LS and HS arm64: dts: qcom: Add msm8916 I2C nodes. arm64: dts: fix i2c pinconf sleep state function arm64: dts: qcom: Enable eMMC on apq8016-sbc board arm64: dts: qcom: Add 8x16 Serial UART1 node arm64: dts: qcom: Add RNG device tree node
This commit is contained in:
Arnd Bergmann
commit
ee04242bec
|
|
@ -19,6 +19,7 @@
|
|||
/ {
|
||||
aliases {
|
||||
serial0 = &blsp1_uart2;
|
||||
serial1 = &blsp1_uart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
|
@ -33,6 +34,31 @@ serial@78b0000 {
|
|||
pinctrl-1 = <&blsp1_uart2_sleep>;
|
||||
};
|
||||
|
||||
i2c@78b6000 {
|
||||
/* On Low speed expansion */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@78b8000 {
|
||||
/* On High speed expansion */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@78ba000 {
|
||||
/* On Low speed expansion */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
spi@78b7000 {
|
||||
/* On High speed expansion */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
spi@78b9000 {
|
||||
/* On Low speed expansion */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
leds {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&msmgpio_leds>,
|
||||
|
|
@ -85,3 +111,7 @@ led@6 {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdhc_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -13,6 +13,30 @@
|
|||
|
||||
&msmgpio {
|
||||
|
||||
blsp1_uart1_default: blsp1_uart1_default {
|
||||
pinmux {
|
||||
function = "blsp_uart1";
|
||||
pins = "gpio0", "gpio1";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio0", "gpio1";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
blsp1_uart1_sleep: blsp1_uart1_sleep {
|
||||
pinmux {
|
||||
function = "gpio";
|
||||
pins = "gpio0", "gpio1";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio0", "gpio1";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
blsp1_uart2_default: blsp1_uart2_default {
|
||||
pinmux {
|
||||
function = "blsp_uart2";
|
||||
|
|
@ -27,7 +51,7 @@ pinconf {
|
|||
|
||||
blsp1_uart2_sleep: blsp1_uart2_sleep {
|
||||
pinmux {
|
||||
function = "blsp_uart2";
|
||||
function = "gpio";
|
||||
pins = "gpio4", "gpio5";
|
||||
};
|
||||
pinconf {
|
||||
|
|
@ -241,6 +265,30 @@ pinconf {
|
|||
};
|
||||
};
|
||||
|
||||
i2c2_default: i2c2_default {
|
||||
pinmux {
|
||||
function = "blsp_i2c2";
|
||||
pins = "gpio6", "gpio7";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio6", "gpio7";
|
||||
drive-strength = <2>;
|
||||
bias-disable = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2_sleep: i2c2_sleep {
|
||||
pinmux {
|
||||
function = "gpio";
|
||||
pins = "gpio6", "gpio7";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio6", "gpio7";
|
||||
drive-strength = <2>;
|
||||
bias-disable = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c4_default: i2c4_default {
|
||||
pinmux {
|
||||
function = "blsp_i2c4";
|
||||
|
|
@ -255,7 +303,7 @@ pinconf {
|
|||
|
||||
i2c4_sleep: i2c4_sleep {
|
||||
pinmux {
|
||||
function = "blsp_i2c4";
|
||||
function = "gpio";
|
||||
pins = "gpio14", "gpio15";
|
||||
};
|
||||
pinconf {
|
||||
|
|
@ -265,6 +313,30 @@ pinconf {
|
|||
};
|
||||
};
|
||||
|
||||
i2c6_default: i2c6_default {
|
||||
pinmux {
|
||||
function = "blsp_i2c6";
|
||||
pins = "gpio22", "gpio23";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio22", "gpio23";
|
||||
drive-strength = <2>;
|
||||
bias-disable = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c6_sleep: i2c6_sleep {
|
||||
pinmux {
|
||||
function = "gpio";
|
||||
pins = "gpio22", "gpio23";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio22", "gpio23";
|
||||
drive-strength = <2>;
|
||||
bias-disable = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhc2_cd_pin {
|
||||
sdc2_cd_on: cd_on {
|
||||
pinmux {
|
||||
|
|
|
|||
|
|
@ -103,6 +103,15 @@ gcc: qcom,gcc@1800000 {
|
|||
reg = <0x1800000 0x80000>;
|
||||
};
|
||||
|
||||
blsp1_uart1: serial@78af000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x78af000 0x200>;
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_uart2: serial@78b0000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x78b0000 0x200>;
|
||||
|
|
@ -225,6 +234,21 @@ blsp_spi6: spi@78ba000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp_i2c2: i2c@78b6000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0x78b6000 0x1000>;
|
||||
interrupts = <GIC_SPI 96 0>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&i2c2_default>;
|
||||
pinctrl-1 = <&i2c2_sleep>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp_i2c4: i2c@78b8000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0x78b8000 0x1000>;
|
||||
|
|
@ -240,6 +264,21 @@ blsp_i2c4: i2c@78b8000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp_i2c6: i2c@78ba000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0x78ba000 0x1000>;
|
||||
interrupts = <GIC_SPI 100 0>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&i2c6_default>;
|
||||
pinctrl-1 = <&i2c6_sleep>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhc_1: sdhci@07824000 {
|
||||
compatible = "qcom,sdhci-msm-v4";
|
||||
reg = <0x07824900 0x11c>, <0x07824000 0x800>;
|
||||
|
|
@ -391,6 +430,13 @@ spmi_bus: spmi@200f000 {
|
|||
interrupt-controller;
|
||||
#interrupt-cells = <4>;
|
||||
};
|
||||
|
||||
rng@22000 {
|
||||
compatible = "qcom,prng";
|
||||
reg = <0x00022000 0x200>;
|
||||
clocks = <&gcc GCC_PRNG_AHB_CLK>;
|
||||
clock-names = "core";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue