iio: adc: stm32: add optional st,min-sample-time-nsecs
STM32 ADC allows each channel to be sampled with a different sampling time, by setting SMPR registers. Basically, value depends on local electrical properties. Selecting correct value for sampling time highly depends on analog source impedance. There is a manual that may help in this process: 'How to get the best ADC accuracy in STM32...' This patch allows to configure minimum sampling time via device tree, either for: - all channels at once: st,min-sample-time-nsecs = <10000>; - independently for each channel (must match "st,adc-channels" list): st,adc-channels = <0 1>; st,min-sample-time-nsecs = <5000 10000>; Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Fabrice Gasnier
Jonathan Cameron
parent
bc8e1f5b21
commit
ee2ac1cdd3
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@ -83,6 +83,8 @@
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#define STM32H7_ADC_IER 0x04
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#define STM32H7_ADC_CR 0x08
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#define STM32H7_ADC_CFGR 0x0C
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#define STM32H7_ADC_SMPR1 0x14
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#define STM32H7_ADC_SMPR2 0x18
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#define STM32H7_ADC_PCSEL 0x1C
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#define STM32H7_ADC_SQR1 0x30
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#define STM32H7_ADC_SQR2 0x34
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@ -151,6 +153,7 @@ enum stm32h7_adc_dmngt {
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#define STM32H7_BOOST_CLKRATE 20000000UL
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#define STM32_ADC_MAX_SQ 16 /* SQ1..SQ16 */
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#define STM32_ADC_MAX_SMP 7 /* SMPx range is [0..7] */
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#define STM32_ADC_TIMEOUT_US 100000
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#define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000))
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@ -227,6 +230,8 @@ struct stm32_adc_regs {
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* @exten: trigger control register & bitfield
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* @extsel: trigger selection register & bitfield
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* @res: resolution selection register & bitfield
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* @smpr: smpr1 & smpr2 registers offset array
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* @smp_bits: smpr1 & smpr2 index and bitfields
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*/
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struct stm32_adc_regspec {
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const u32 dr;
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@ -236,6 +241,8 @@ struct stm32_adc_regspec {
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const struct stm32_adc_regs exten;
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const struct stm32_adc_regs extsel;
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const struct stm32_adc_regs res;
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const u32 smpr[2];
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const struct stm32_adc_regs *smp_bits;
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};
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struct stm32_adc;
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@ -251,6 +258,7 @@ struct stm32_adc;
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* @start_conv: routine to start conversions
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* @stop_conv: routine to stop conversions
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* @unprepare: optional unprepare routine (disable, power-down)
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* @smp_cycles: programmable sampling time (ADC clock cycles)
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*/
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struct stm32_adc_cfg {
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const struct stm32_adc_regspec *regs;
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@ -262,6 +270,7 @@ struct stm32_adc_cfg {
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void (*start_conv)(struct stm32_adc *, bool dma);
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void (*stop_conv)(struct stm32_adc *);
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void (*unprepare)(struct stm32_adc *);
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const unsigned int *smp_cycles;
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};
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/**
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@ -283,6 +292,7 @@ struct stm32_adc_cfg {
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* @rx_dma_buf: dma rx buffer bus address
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* @rx_buf_sz: dma rx buffer size
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* @pcsel bitmask to preselect channels on some devices
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* @smpr_val: sampling time settings (e.g. smpr1 / smpr2)
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* @cal: optional calibration data on some devices
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*/
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struct stm32_adc {
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@ -303,6 +313,7 @@ struct stm32_adc {
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dma_addr_t rx_dma_buf;
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unsigned int rx_buf_sz;
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u32 pcsel;
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u32 smpr_val[2];
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struct stm32_adc_calib cal;
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};
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@ -431,6 +442,39 @@ static struct stm32_adc_trig_info stm32f4_adc_trigs[] = {
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{}, /* sentinel */
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};
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/**
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* stm32f4_smp_bits[] - describe sampling time register index & bit fields
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* Sorted so it can be indexed by channel number.
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*/
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static const struct stm32_adc_regs stm32f4_smp_bits[] = {
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/* STM32F4_ADC_SMPR2: smpr[] index, mask, shift for SMP0 to SMP9 */
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{ 1, GENMASK(2, 0), 0 },
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{ 1, GENMASK(5, 3), 3 },
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{ 1, GENMASK(8, 6), 6 },
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{ 1, GENMASK(11, 9), 9 },
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{ 1, GENMASK(14, 12), 12 },
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{ 1, GENMASK(17, 15), 15 },
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{ 1, GENMASK(20, 18), 18 },
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{ 1, GENMASK(23, 21), 21 },
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{ 1, GENMASK(26, 24), 24 },
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{ 1, GENMASK(29, 27), 27 },
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/* STM32F4_ADC_SMPR1, smpr[] index, mask, shift for SMP10 to SMP18 */
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{ 0, GENMASK(2, 0), 0 },
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{ 0, GENMASK(5, 3), 3 },
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{ 0, GENMASK(8, 6), 6 },
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{ 0, GENMASK(11, 9), 9 },
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{ 0, GENMASK(14, 12), 12 },
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{ 0, GENMASK(17, 15), 15 },
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{ 0, GENMASK(20, 18), 18 },
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{ 0, GENMASK(23, 21), 21 },
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{ 0, GENMASK(26, 24), 24 },
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};
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/* STM32F4 programmable sampling time (ADC clock cycles) */
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static const unsigned int stm32f4_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = {
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3, 15, 28, 56, 84, 112, 144, 480,
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};
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static const struct stm32_adc_regspec stm32f4_adc_regspec = {
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.dr = STM32F4_ADC_DR,
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.ier_eoc = { STM32F4_ADC_CR1, STM32F4_EOCIE },
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@ -440,6 +484,8 @@ static const struct stm32_adc_regspec stm32f4_adc_regspec = {
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.extsel = { STM32F4_ADC_CR2, STM32F4_EXTSEL_MASK,
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STM32F4_EXTSEL_SHIFT },
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.res = { STM32F4_ADC_CR1, STM32F4_RES_MASK, STM32F4_RES_SHIFT },
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.smpr = { STM32F4_ADC_SMPR1, STM32F4_ADC_SMPR2 },
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.smp_bits = stm32f4_smp_bits,
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};
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static const struct stm32_adc_regs stm32h7_sq[STM32_ADC_MAX_SQ + 1] = {
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@ -483,6 +529,40 @@ static struct stm32_adc_trig_info stm32h7_adc_trigs[] = {
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{},
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};
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/**
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* stm32h7_smp_bits - describe sampling time register index & bit fields
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* Sorted so it can be indexed by channel number.
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*/
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static const struct stm32_adc_regs stm32h7_smp_bits[] = {
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/* STM32H7_ADC_SMPR1, smpr[] index, mask, shift for SMP0 to SMP9 */
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{ 0, GENMASK(2, 0), 0 },
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{ 0, GENMASK(5, 3), 3 },
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{ 0, GENMASK(8, 6), 6 },
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{ 0, GENMASK(11, 9), 9 },
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{ 0, GENMASK(14, 12), 12 },
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{ 0, GENMASK(17, 15), 15 },
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{ 0, GENMASK(20, 18), 18 },
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{ 0, GENMASK(23, 21), 21 },
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{ 0, GENMASK(26, 24), 24 },
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{ 0, GENMASK(29, 27), 27 },
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/* STM32H7_ADC_SMPR2, smpr[] index, mask, shift for SMP10 to SMP19 */
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{ 1, GENMASK(2, 0), 0 },
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{ 1, GENMASK(5, 3), 3 },
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{ 1, GENMASK(8, 6), 6 },
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{ 1, GENMASK(11, 9), 9 },
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{ 1, GENMASK(14, 12), 12 },
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{ 1, GENMASK(17, 15), 15 },
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{ 1, GENMASK(20, 18), 18 },
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{ 1, GENMASK(23, 21), 21 },
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{ 1, GENMASK(26, 24), 24 },
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{ 1, GENMASK(29, 27), 27 },
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};
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/* STM32H7 programmable sampling time (ADC clock cycles, rounded down) */
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static const unsigned int stm32h7_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = {
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1, 2, 8, 16, 32, 64, 387, 810,
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};
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static const struct stm32_adc_regspec stm32h7_adc_regspec = {
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.dr = STM32H7_ADC_DR,
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.ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE },
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@ -492,6 +572,8 @@ static const struct stm32_adc_regspec stm32h7_adc_regspec = {
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.extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK,
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STM32H7_EXTSEL_SHIFT },
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.res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT },
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.smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 },
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.smp_bits = stm32h7_smp_bits,
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};
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/**
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@ -933,6 +1015,7 @@ static void stm32h7_adc_unprepare(struct stm32_adc *adc)
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* @scan_mask: channels to be converted
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*
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* Conversion sequence :
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* Apply sampling time settings for all channels.
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* Configure ADC scan sequence based on selected channels in scan_mask.
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* Add channels to SQR registers, from scan_mask LSB to MSB, then
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* program sequence len.
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@ -946,6 +1029,10 @@ static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev,
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u32 val, bit;
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int i = 0;
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/* Apply sampling time settings */
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stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]);
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stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]);
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for_each_set_bit(bit, scan_mask, indio_dev->masklength) {
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chan = indio_dev->channels + bit;
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/*
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@ -1079,6 +1166,7 @@ static const struct iio_enum stm32_adc_trig_pol = {
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* @res: conversion result
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*
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* The function performs a single conversion on a given channel:
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* - Apply sampling time settings
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* - Program sequencer with one channel (e.g. in SQ1 with len = 1)
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* - Use SW trigger
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* - Start conversion, then wait for interrupt completion.
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@ -1103,6 +1191,10 @@ static int stm32_adc_single_conv(struct iio_dev *indio_dev,
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return ret;
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}
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/* Apply sampling time settings */
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stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]);
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stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]);
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/* Program chan number in regular sequence (SQ1) */
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val = stm32_adc_readl(adc, regs->sqr[1].reg);
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val &= ~regs->sqr[1].mask;
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@ -1507,10 +1599,28 @@ static int stm32_adc_of_get_resolution(struct iio_dev *indio_dev)
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return 0;
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}
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static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns)
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{
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const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel];
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u32 period_ns, shift = smpr->shift, mask = smpr->mask;
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unsigned int smp, r = smpr->reg;
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/* Determine sampling time (ADC clock cycles) */
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period_ns = NSEC_PER_SEC / adc->common->rate;
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for (smp = 0; smp <= STM32_ADC_MAX_SMP; smp++)
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if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns)
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break;
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if (smp > STM32_ADC_MAX_SMP)
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smp = STM32_ADC_MAX_SMP;
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/* pre-build sampling time registers (e.g. smpr1, smpr2) */
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adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift);
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}
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static void stm32_adc_chan_init_one(struct iio_dev *indio_dev,
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struct iio_chan_spec *chan,
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const struct stm32_adc_chan_spec *channel,
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int scan_index)
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int scan_index, u32 smp)
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{
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struct stm32_adc *adc = iio_priv(indio_dev);
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@ -1526,6 +1636,9 @@ static void stm32_adc_chan_init_one(struct iio_dev *indio_dev,
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chan->scan_type.storagebits = 16;
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chan->ext_info = stm32_adc_ext_info;
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/* Prepare sampling time settings */
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stm32_adc_smpr_init(adc, chan->channel, smp);
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/* pre-build selected channels mask */
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adc->pcsel |= BIT(chan->channel);
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}
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@ -1538,8 +1651,8 @@ static int stm32_adc_chan_of_init(struct iio_dev *indio_dev)
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struct property *prop;
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const __be32 *cur;
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struct iio_chan_spec *channels;
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int scan_index = 0, num_channels;
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u32 val;
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int scan_index = 0, num_channels, ret;
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u32 val, smp = 0;
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num_channels = of_property_count_u32_elems(node, "st,adc-channels");
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if (num_channels < 0 ||
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@ -1548,6 +1661,13 @@ static int stm32_adc_chan_of_init(struct iio_dev *indio_dev)
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return num_channels < 0 ? num_channels : -EINVAL;
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}
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/* Optional sample time is provided either for each, or all channels */
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ret = of_property_count_u32_elems(node, "st,min-sample-time-nsecs");
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if (ret > 1 && ret != num_channels) {
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dev_err(&indio_dev->dev, "Invalid st,min-sample-time-nsecs\n");
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return -EINVAL;
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}
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channels = devm_kcalloc(&indio_dev->dev, num_channels,
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sizeof(struct iio_chan_spec), GFP_KERNEL);
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if (!channels)
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@ -1558,9 +1678,19 @@ static int stm32_adc_chan_of_init(struct iio_dev *indio_dev)
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dev_err(&indio_dev->dev, "Invalid channel %d\n", val);
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return -EINVAL;
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}
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/*
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* Using of_property_read_u32_index(), smp value will only be
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* modified if valid u32 value can be decoded. This allows to
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* get either no value, 1 shared value for all indexes, or one
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* value per channel.
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*/
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of_property_read_u32_index(node, "st,min-sample-time-nsecs",
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scan_index, &smp);
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stm32_adc_chan_init_one(indio_dev, &channels[scan_index],
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&adc_info->channels[val],
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scan_index);
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scan_index, smp);
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scan_index++;
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}
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@ -1755,6 +1885,7 @@ static const struct stm32_adc_cfg stm32f4_adc_cfg = {
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.clk_required = true,
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.start_conv = stm32f4_adc_start_conv,
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.stop_conv = stm32f4_adc_stop_conv,
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.smp_cycles = stm32f4_adc_smp_cycles,
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};
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static const struct stm32_adc_cfg stm32h7_adc_cfg = {
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@ -1766,6 +1897,7 @@ static const struct stm32_adc_cfg stm32h7_adc_cfg = {
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.stop_conv = stm32h7_adc_stop_conv,
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.prepare = stm32h7_adc_prepare,
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.unprepare = stm32h7_adc_unprepare,
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.smp_cycles = stm32h7_adc_smp_cycles,
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};
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static const struct of_device_id stm32_adc_of_match[] = {
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